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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Am Tue, Feb 18, 2025 at 11:25:28PM +0000 schrieb Michael: > > TLC (tri-level cells) > >=20 > > Hey, what if we do 8 different charge levels! Now you get 4 bits per > > cell. Even harder to do, even less reliable... > >=20 > >=20 > > QLC (quad-level cells) > >=20 > > [I think you see where this is going] >=20 > Yep, SLC > MLC > TLC > QLC in terms of performance, reliability, longevit= y and=20 > price. The phenomenal decrease in price per GB/TB over time is just that= =2E =20 > Phenomenal. For reasons Grant explained it comes with measured reduction= in=20 > reliability and longevity. > Since they come with fast(er) DRAM cache which to=20 > some extent masks the underlying NAND performance, with other things bein= g=20 > equal it makes sense to choose one with faster/larger DRAM. Small correction: the DRAM is not for fast write performance. That is what= =20 SLC cache is for: a small(ish) part of the TLC or QLC flash is used in SLC= =20 mode, so the SSD can ingest data faster. In time of idleness, the SSD=20 controller starts =E2=80=9Cswapping out=E2=80=9D the content of the SLC cac= he into its slow=20 TLC/QLC storage. The DRAM=E2=80=99s single purpose is to hold the flash translation layer, i= =2Ee. the=20 mapping of logical storage area to physical flash cell. Otherwise it would= =20 have to constantly be written during operation, which will make such=20 operation slower, epecially when dealing with many small files. --=20 Gr=C3=BC=C3=9Fe | Greetings | Salut | Qapla=E2=80=99 Please do not share anything from, with or about me on any social network. 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