Am Tue, Feb 18, 2025 at 11:25:28PM +0000 schrieb Michael:

> > TLC (tri-level cells)
> > 
> > Hey, what if we do 8 different charge levels! Now you get 4 bits per
> > cell.  Even harder to do, even less reliable...
> > 
> > 
> > QLC (quad-level cells)
> > 
> > [I think you see where this is going]
> 
> Yep, SLC > MLC > TLC > QLC in terms of performance, reliability, longevity and 
> price.  The phenomenal decrease in price per GB/TB over time is just that.  
> Phenomenal.  For reasons Grant explained it comes with measured reduction in 
> reliability and longevity.

> Since they come with fast(er) DRAM cache which to 
> some extent masks the underlying NAND performance, with other things being 
> equal it makes sense to choose one with faster/larger DRAM.

Small correction: the DRAM is not for fast write performance. That is what 
SLC cache is for: a small(ish) part of the TLC or QLC flash is used in SLC 
mode, so the SSD can ingest data faster. In time of idleness, the SSD 
controller starts “swapping out” the content of the SLC cache into its slow 
TLC/QLC storage.

The DRAM’s single purpose is to hold the flash translation layer, i.e. the 
mapping of logical storage area to physical flash cell. Otherwise it would 
have to constantly be written during operation, which will make such 
operation slower, epecially when dealing with many small files.

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