From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gentoo.org (pigeon.gentoo.org [208.92.234.80]) by finch.gentoo.org (Postfix) with ESMTP id A2EEE138CC5 for ; Mon, 23 Mar 2015 22:49:08 +0000 (UTC) Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 78CF7E0877; Mon, 23 Mar 2015 22:49:04 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by pigeon.gentoo.org (Postfix) with ESMTPS id 47174E06FE for ; Mon, 23 Mar 2015 22:49:03 +0000 (UTC) Received: from mail-ie0-f171.google.com (mail-ie0-f171.google.com [209.85.223.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: floppym) by smtp.gentoo.org (Postfix) with ESMTPSA id 14276340A46 for ; Mon, 23 Mar 2015 22:49:02 +0000 (UTC) Received: by ieclw3 with SMTP id lw3so47821829iec.2 for ; Mon, 23 Mar 2015 15:48:59 -0700 (PDT) X-Received: by 10.107.6.11 with SMTP id 11mr2212217iog.34.1427150939868; Mon, 23 Mar 2015 15:48:59 -0700 (PDT) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-user@lists.gentoo.org Reply-to: gentoo-user@lists.gentoo.org MIME-Version: 1.0 Received: by 10.64.128.168 with HTTP; Mon, 23 Mar 2015 15:48:39 -0700 (PDT) In-Reply-To: <3086055.ZU6mplhdnj@navi> References: <20150319015612.GA7416@waltdnes.org> <20150324015104.GA32732@waltdnes.org> <3086055.ZU6mplhdnj@navi> From: Mike Gilbert Date: Mon, 23 Mar 2015 18:48:39 -0400 Message-ID: Subject: Re: [gentoo-user] Will a 64-bit-no-multilib machine cross-compile 32-bit code? To: gentoo-user@lists.gentoo.org Content-Type: text/plain; charset=UTF-8 X-Archives-Salt: dd5cf08b-6405-4b24-9677-31764394c12c X-Archives-Hash: 6741d2e5009717c6a321eb6dc7b02013 On Mon, Mar 23, 2015 at 6:41 PM, Fernando Rodriguez wrote: > On Monday, March 23, 2015 6:18:46 PM Mike Gilbert wrote: >> On Mon, Mar 23, 2015 at 9:51 PM, Walter Dnes wrote: >> > On Sun, Mar 22, 2015 at 09:25:53PM -0400, Fernando Rodriguez wrote >> > >> >> I guess gcc devs are careful when using the model numbers (Intel >> >> lists 3 for Atoms, gcc uses only two so that may account for the >> >> models I mentioned) but the chance of error is there. The -mno-xxx >> >> flags would safeguard against it. >> > >> > I have one of the earliest Atom chips. Some people have a hard time >> > believing this, but it's a 32-bit-only chip; a couple of lines from >> > /proc/cpuinfo >> > >> > model name : Intel(R) Atom(TM) CPU Z520 @ 1.33GHz >> > address sizes : 32 bits physical, 32 bits virtual >> > >> > Intel gives the CPU's specs at... >> > >> > http://ark.intel.com/products/35466/Intel-Atom-Processor-Z520-512K-Cache-1_33-GHz-533-MHz-FSB >> > >> > ...where it specifically says... >> > >> > Intel 64 # No >> > >> > I want to make absolutely certain that "illegal instructions" are not >> > compiled for it. >> >> You will probably need to add -m32 to CFLAGS to avoid building 64-bit >> objects on the 64-bit machine. >> > > Your CPU is an example of what I'm saying, not just because it doesn't have 64 > bit extensions but because it doesn't have MMX (at least according to the > specs) and according to the GCC manual -march=atom means: "Intel Atom CPU with > 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set > support." So I guess it's more common than I thought. > > So you may also want to add -mno-mmx to be sure. GCC does check for mmx but it > doesn't not use it on the output (probably a bug?). > It's much more likely that Intel's website doesn't bother including MMX because it is so damn old that nobody cares. /proc/cpuinfo would be a more reliable source of data.