From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gentoo.org (pigeon.gentoo.org [208.92.234.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by finch.gentoo.org (Postfix) with ESMTPS id 14A51139083 for ; Tue, 5 Dec 2017 19:09:47 +0000 (UTC) Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 7F816E1030; Tue, 5 Dec 2017 19:09:40 +0000 (UTC) Received: from mail-lf0-x236.google.com (mail-lf0-x236.google.com [IPv6:2a00:1450:4010:c07::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by pigeon.gentoo.org (Postfix) with ESMTPS id E4B40E0FFA for ; Tue, 5 Dec 2017 19:09:39 +0000 (UTC) Received: by mail-lf0-x236.google.com with SMTP id 74so1550016lfs.0 for ; Tue, 05 Dec 2017 11:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mclure-org.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=xiKH6MucncheZxaivCCU6TJ8CU9rCFck6G6ogGmN8x0=; b=qNbeKCmLRihxLXDPBsA/diMZMuvGEy226v49BhQOYIP9kgopMWIgiRk5+G6fUdFpQo 67oQ1NEP8LWEy0XcshxAaAbg4VyJzpSG+Qkksuel1iqRz9wpKEFYqptRhcSDAizHT0Lq PzjBAdR9SyBkAucb5eS07PEjYAj5TpxjxnJPYyKVrLVA5XJUWmyktv1l2q4xZmozr/3x x8MBXIWr4tVGdsrR2IgvHz2T6o7e+PFQl2iPUCZFzfP5+NtT7S8TpPJJkFLEQ3c8DxAv yRkdZ0UDt4/x7ftTDiAOrknWBtTtCQuiYOfqM1SeJrR1P2RRt9mMlv+iwzv2R36cNsPl W34w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=xiKH6MucncheZxaivCCU6TJ8CU9rCFck6G6ogGmN8x0=; b=GJQV1mRHB8v3+PRKqQbTbro5mXr0/6dMXOzo6XIvi+2kVV8y2Nzf/bLLyKofIbOWh3 qRpYbMHKzSWUPdsy7emLc+jPPQByRao7sAyIdpe4c6XzN8BTcsB4xZYhKXhoud/rD/yi J+lFc221ndN0SjWjN/EzAx1cgHqg951BFlXKDz0gpDYvnuNfMY4pTcqLab5zOP8ItCCT UI8V0N5e4cNqQF41aYNO8khRWpV8ID0gMTkcLGj8hkbzzfWGAldBhB+dWMXQSuLpl8fi zlRu4A25oXFUWLx3ByFDIhafGsLD7qA4jgpyc3MeQS1Gi8pwLPr+q6rP+6pvyYaHR770 a39w== X-Gm-Message-State: AJaThX7NHS0qO1Sx3THs/d6YiWE+dCkEgrtClOj/H+rCBTGXaXD7mbIX To+8Xbd56Q1zLdUnTDWAWepIGdE= X-Google-Smtp-Source: AGs4zMZHEUG61H6lQ3v9ggmsCnQ2TSPOe9++z3zjALWI/kWT+d0M+WLVnDYTQYSEvBmLbCgWu4adPA== X-Received: by 10.46.87.74 with SMTP id r10mr12297973ljd.43.1512500977747; Tue, 05 Dec 2017 11:09:37 -0800 (PST) Received: from mail-lf0-f54.google.com (mail-lf0-f54.google.com. [209.85.215.54]) by smtp.gmail.com with ESMTPSA id u73sm153469lfg.65.2017.12.05.11.09.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Dec 2017 11:09:36 -0800 (PST) Received: by mail-lf0-f54.google.com with SMTP id f20so1544073lfe.3 for ; Tue, 05 Dec 2017 11:09:36 -0800 (PST) X-Received: by 10.46.80.73 with SMTP id v9mr11522919ljd.93.1512500976488; Tue, 05 Dec 2017 11:09:36 -0800 (PST) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-user@lists.gentoo.org Reply-to: gentoo-user@lists.gentoo.org MIME-Version: 1.0 Received: by 10.25.78.28 with HTTP; Tue, 5 Dec 2017 11:09:35 -0800 (PST) In-Reply-To: <20171203080852.GB30078@waltdnes.org> References: <20171203080852.GB30078@waltdnes.org> From: Manuel McLure Date: Tue, 5 Dec 2017 11:09:35 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [gentoo-user] CFLAGS for both AMD64 and Intel? To: gentoo-user@lists.gentoo.org Content-Type: multipart/alternative; boundary="f403045fc0ba6d19a2055f9c933c" X-Archives-Salt: 90b0e048-3f06-469b-a9f5-db8d6fbd2b3d X-Archives-Hash: 0e361c9fd43c74e7ced0ebbdb239b08c --f403045fc0ba6d19a2055f9c933c Content-Type: text/plain; charset="UTF-8" On Sun, Dec 3, 2017 at 12:08 AM, Walter Dnes wrote: > > https://gcc.gnu.org/onlinedocs/gcc-6.4.0/gcc/x86-Options.html#x86-Options > lists what instruction sets gcc expects for any "-march=" > > I would suggest rebuilding with... > > CFLAGS="-march=nocona -O2 -pipe" > CPU_FLAGS_X86="mmx sse sse2 sse3" > > nocona was the first Intel cpu to support AMD64 instructions, and it's > the newest Intel that does not exceed your AMD. The next Intel cpu, the > "core2" supports ssse3 which your AMD does not (count the "s"'s... very > carefully; sse3 != ssse3). > > Thanks! I have successfully rebuilt the system with "-march=nocona -O2 -pipe" (and switched to gcc 6.4.0/profile 17 while I was at it) and everything seems to be running fine. Hopefully I can pick up a micro-ATX LGA1156 motherboard for cheap and can do the processor upgrade soon. -- Manuel A. McLure WW1FA ...for in Ulthar, according to an ancient and significant law, no man may kill a cat. -- H.P. Lovecraft --f403045fc0ba6d19a2055f9c933c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On S= un, Dec 3, 2017 at 12:08 AM, Walter Dnes <waltdnes@waltdnes.org>= ; wrote:

https://gcc.gnu.org/= onlinedocs/gcc-6.4.0/gcc/x86-Options.html#x86-Options
lists what instruction sets gcc expects for any "-march=3D<whatever= >"

=C2=A0 I would suggest rebuilding with...

CFLAGS=3D"-march=3Dnocona -O2 -pipe"
CPU_FLAGS_X86=3D"mmx sse sse2 sse3"

=C2=A0 nocona was the first Intel cpu to support AMD64 instructions, and it= 's
the newest Intel that does not exceed your AMD.=C2=A0 The next Intel cpu, t= he
"core2" supports ssse3 which your AMD does not (count the "s= "'s... very
carefully; sse3 !=3D ssse3).


Thanks! I have successfully rebuilt the system with = "-march=3Dnocona -O2 -pipe" (and switched to gcc 6.4.0/profile 17= while I was at it) and everything seems to be running fine. Hopefully I ca= n pick up a micro-ATX LGA1156 motherboard for cheap and can do the processo= r upgrade soon.

--
Manuel A. McLure WW1FA <manuel@mclure.org> &= lt;http://www.mclure.or= g>
...for in Ulthar, according to an ancient and significant law,=
no man may kill a cat.=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0=C2=A0 -- H.P. Lovecraft
--f403045fc0ba6d19a2055f9c933c--