From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gentoo.org (pigeon.gentoo.org [208.92.234.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by finch.gentoo.org (Postfix) with ESMTPS id CB5FC138334 for ; Tue, 1 Oct 2019 11:49:01 +0000 (UTC) Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 6E965E098A; Tue, 1 Oct 2019 11:48:57 +0000 (UTC) Received: from smarthost01d.mail.zen.net.uk (smarthost01d.mail.zen.net.uk [212.23.1.7]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by pigeon.gentoo.org (Postfix) with ESMTPS id ECEA2E0968 for ; Tue, 1 Oct 2019 11:48:56 +0000 (UTC) Received: from [62.3.120.142] (helo=NeddySeagoon_Static) by smarthost01d.mail.zen.net.uk with esmtpsa (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1iFGeF-00057u-Gb for gentoo-dev@lists.gentoo.org; Tue, 01 Oct 2019 11:48:55 +0000 Date: Tue, 01 Oct 2019 12:48:39 +0100 From: Roy Bamford Subject: Re: [gentoo-dev] Need ARM/AArch64 test data for cpuid2cpuflags To: gentoo-dev@lists.gentoo.org In-Reply-To: (from mgorny@gentoo.org on Tue Sep 10 21:44:54 2019) X-Mailer: Balsa 2.5.6 Message-Id: Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-dev@lists.gentoo.org Reply-to: gentoo-dev@lists.gentoo.org X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply MIME-Version: 1.0 Content-Type: multipart/signed; micalg=PGP-SHA256; protocol="application/pgp-signature"; boundary="=-3xYBLvIMdHJWAmap/JcH" X-Originating-smarthost01d-IP: [62.3.120.142] Feedback-ID: 62.3.120.142 X-Archives-Salt: c0e86ff8-bd98-4349-98e0-057dd7711c50 X-Archives-Hash: 0665188066e39070f1a430e85bad51c5 --=-3xYBLvIMdHJWAmap/JcH Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2019.09.10 21:44, Micha=C5=82 G=C3=B3rny wrote: > Hi, everyone. >=20 > I've recently (finally!) started adding tests to cpuid2cpuflags.=20 > Tests > are based on mocked syscalls that return arch-specific data read from > text files. So far I've got x86 and ppc covered, and now I'd like to > add tests for various arm hardware. Since ARM covers a pretty broad > range of hardware, I'd use as much data as possible, especially from > different ARM generations. >=20 > If you have an ARM board and would like to help, please: >=20 > wget https://dev.gentoo.org/~mgorny/dist/cpuid2cpuflags-7-dev.tar.bz2 > tar -xf cpuid2cpuflags-7-dev.tar.bz2 > cd cpuid2cpuflags-7-dev > ./configure > make hwcap-dump > ./hwcap-dump >=20 > and send me the output along with 'uname -m'. TIA! >=20 > --=20 > Best regards, > Micha=C5=82 G=C3=B3rny >=20 >=20 Team, this is going to be a long rambling tale of woe. Sorry in advance. On arm64 cpuid2cpuflags-8 tells me =20 Pi4_~arm64 /usr/portage # cpuid2cpuflags=20 CPU_FLAGS_ARM: edsp neon thumb vfp vfpv3 vfpv4 vfp-d32 crc32 v4 v5 v6 v7 v8= thumb2 but by chance I hit=20 [Bug 695854] net-misc/freerdp-2.0.0_rc4 on arm64 - aarch64-unknown-linux-gn= u-gcc: error: unrecognized command line option =E2=80=98-mfpu=3Dneon=E2=80= =99 The 32 bit arm instruction set is optional on arm64. The 64 bit Raspberry Pis all have it The Cavium Thunder does not. It is unlikely that there will ever be a multilib arm64. Only a subset of arm64 could ever support it, so should we be using CPU_FLAGS_ARM to cover arm64 too? There is nothing in the name. Its the content that matters. On a Pi4 in 64 bit mode, cpuinfo shows Pi4_~arm64 /usr/portage # cat /proc/cpuinfo=20 processor : 0 BogoMIPS : 108.00 Features : fp asimd evtstrm crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd08 CPU revision : 3 In 32 bit mode, the same CPU shows $ cat pi4_32.txt=20 processor : 0 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 108.00 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vf= pd32 lpae evtstrm crc32=20 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xd08 CPU revision : 3 Cavium (64 bit) arm64-build / # cat /proc/cpuinfo=20 processor : 0 BogoMIPS : 200.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x43 CPU architecture: 8 CPU variant : 0x1 CPU part : 0x0a1 CPU revision : 1 The Cavium does not have any 32 bit instructions. =46rom bug 695854, CPU_FLAGS_ARM: neon is not correct on the Cavium. I suspect that the other 32 bit flags will fail there, as it does not have = them but they might work on the Pi, as it does. Other than pointing out the problem, I don't know how to test further.=20 Guidance welcome. --=20 Regards, Roy Bamford (Neddyseagoon) a member of elections gentoo-ops forum-mods arm64= --=-3xYBLvIMdHJWAmap/JcH Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEsOrcx0gZrrCMwJzo/xJODTqpeT4FAl2TPRoACgkQ/xJODTqp eT6bvQgAjdJHwRXjAj85Fa1OGjq4mNUG7yS1pXoAQkvCm5bsfUdWjJEkMJKF3CnC /ta75GNjk4E7sKz6aElT3v9hjnpIIngjfydg1+xZLyDq0E7z1qhIwNborAJxPN2d 28/w7+vno4lMV5Bxn0OZJQ3cVB9oavwpI0aHXRiQqlBAHO0m7IcZhYXUJWIJwEw1 Fu+fL/x09UqQrgJ63/ZRxJrasSDY4fdUGNquAvD0jSlSjTRfmWZuM/XN8FmSzX7S rnlvcRkYCeq6foLUFEl+LKrZNhRl3bMgd2jMUsKUwmhWzTG5xGzurdt+UwSEI6OF iI1oyqCLcEfTUyeKpfOGGxcBFaWJPQ== =wcYr -----END PGP SIGNATURE----- --=-3xYBLvIMdHJWAmap/JcH--