From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pigeon.gentoo.org ([208.92.234.80] helo=lists.gentoo.org) by finch.gentoo.org with esmtp (Exim 4.60) (envelope-from ) id 1QiCFH-0004PJ-54 for garchives@archives.gentoo.org; Sat, 16 Jul 2011 21:17:55 +0000 Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 7D57521C041; Sat, 16 Jul 2011 21:17:45 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by pigeon.gentoo.org (Postfix) with ESMTP id 34E2121C020 for ; Sat, 16 Jul 2011 21:17:44 +0000 (UTC) Received: from pelican.gentoo.org (unknown [66.219.59.40]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id 3CBD81B4006 for ; Sat, 16 Jul 2011 21:17:44 +0000 (UTC) Received: from localhost.localdomain (localhost [127.0.0.1]) by pelican.gentoo.org (Postfix) with ESMTP id 90FFF8003F for ; Sat, 16 Jul 2011 21:17:43 +0000 (UTC) From: "Matt Turner" To: gentoo-commits@lists.gentoo.org Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Matt Turner" Message-ID: Subject: [gentoo-commits] proj/catalyst:master commit in: modules/catalyst/arch/ X-VCS-Repository: proj/catalyst X-VCS-Files: modules/catalyst/arch/mips.py X-VCS-Directories: modules/catalyst/arch/ X-VCS-Committer: mattst88 X-VCS-Committer-Name: Matt Turner X-VCS-Revision: fe2c40a88e1240354fba138e1e0039a89227d47f Date: Sat, 16 Jul 2011 21:17:43 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: quoted-printable X-Archives-Salt: X-Archives-Hash: d856a607dd3bcb612800d4f67caa0c3e commit: fe2c40a88e1240354fba138e1e0039a89227d47f Author: Matt Turner gmail com> AuthorDate: Sat Jul 16 18:31:56 2011 +0000 Commit: Matt Turner gmail com> CommitDate: Sat Jul 16 18:31:56 2011 +0000 URL: http://git.overlays.gentoo.org/gitweb/?p=3Dproj/catalyst.git;= a=3Dcommit;h=3Dfe2c40a8 mips.py: add mips32 and mips64 builder classes Signed-off-by: Matt Turner gmail.com> --- modules/catalyst/arch/mips.py | 72 +++++++++++++++++++++++++++++++++++= ++++++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/modules/catalyst/arch/mips.py b/modules/catalyst/arch/mips.p= y index 16ec207..5d43842 100644 --- a/modules/catalyst/arch/mips.py +++ b/modules/catalyst/arch/mips.py @@ -41,6 +41,12 @@ class arch_mips1(generic_mips): generic_mips.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips1 -mabi=3D32 -pipe" =20 +class arch_mips32(generic_mips): + "Builder class for MIPS 32 [Big-endian]" + def __init__(self,myspec): + generic_mips.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips32 -mfix-24k -mabi=3D32 -p= ipe" + class arch_mips3(generic_mips): "Builder class for MIPS III [Big-endian]" def __init__(self,myspec): @@ -91,12 +97,43 @@ class arch_mips4_multilib(generic_mips64,generic_mult= ilib): generic_multilib.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips4 -pipe" =20 +class arch_mips64(generic_mips64): + "Builder class for MIPS 64 [Big-endian]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3D32 -pipe" + +class arch_mips64_n32(generic_mips64): + "Builder class for MIPS 64 [Big-endian N32]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3Dn32 -pipe" + +class arch_mips64_n64(generic_mips64): + "Builder class for MIPS 64 [Big-endian N64]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3D64 -pipe" + +class arch_mips64_multilib(generic_mips64,generic_multilib): + "Builder class for MIPS 64 [Big-endian multilib]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -pipe" + class arch_mipsel1(generic_mipsel): "Builder class for all MIPS I [Little-endian]" def __init__(self,myspec): generic_mipsel.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips1 -mabi=3D32 -pipe" =20 +class arch_mips32el(generic_mipsel): + "Builder class for all MIPS 32 [Little-endian]" + def __init__(self,myspec): + generic_mipsel.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips32 -mfix-24k -mabi=3D32 -p= ipe" + class arch_mipsel3(generic_mipsel): "Builder class for all MIPS III [Little-endian]" def __init__(self,myspec): @@ -171,6 +208,31 @@ class arch_mipsel4_multilib(generic_mips64el,generic= _multilib): generic_multilib.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips4 -pipe" =20 +class arch_mips64el(generic_mips64el): + "Builder class for all MIPS 64 [Little-endian]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3D32 -pipe" + +class arch_mips64el_n32(generic_mips64el): + "Builder class for all MIPS 64 [Little-endian N32]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3Dn32 -pipe" + +class arch_mips64el_n64(generic_mips64el): + "Builder class for MIPS 64 [Little-endian N64]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -mabi=3D64 -pipe" + +class arch_mips64el_multilib(generic_mips64el,generic_multilib): + "Builder class for MIPS 64 [Little-endian multilib]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dmips64 -pipe" + class arch_cobalt(generic_mipsel): "Builder class for all cobalt [Little-endian]" def __init__(self,myspec): @@ -190,6 +252,7 @@ _subarch_map =3D { "cobalt_n32" : arch_cobalt_n32, "mips" : arch_mips1, "mips1" : arch_mips1, + "mips32" : arch_mips32, "mips3" : arch_mips3, "mips3_n32" : arch_mips3_n32, "mips3_n64" : arch_mips3_n64, @@ -198,8 +261,13 @@ _subarch_map =3D { "mips4_n32" : arch_mips4_n32, "mips4_n64" : arch_mips4_n64, "mips4_multilib": arch_mips4_multilib, + "mips64" : arch_mips64, + "mips64_n32" : arch_mips64_n32, + "mips64_n64" : arch_mips64_n64, + "mips64_multilib" : arch_mips64_multilib, "mipsel" : arch_mipsel1, "mipsel1" : arch_mipsel1, + "mips32el" : arch_mips32el, "mipsel3" : arch_mipsel3, "mipsel3_n32" : arch_mipsel3_n32, "mipsel3_n64" : arch_mipsel3_n64, @@ -208,6 +276,10 @@ _subarch_map =3D { "mipsel4_n32" : arch_mipsel4_n32, "mipsel4_n64" : arch_mipsel4_n64, "mipsel4_multilib" : arch_mipsel4_multilib, + "mips64el" : arch_mips64el, + "mips64el_n32" : arch_mips64el_n32, + "mips64el_n64" : arch_mips64el_n64, + "mips64el_multilib" : arch_mips64el_multilib, "loongson2e" : arch_loongson2e, "loongson2e_n32" : arch_loongson2e_n32, "loongson2f" : arch_loongson2f,