[gentoo-commits] proj/qemu-kvm:qemu-kvm-0.13.0-gentoo commit in: target-arm/

[gentoo-commits] proj/qemu-kvm:qemu-kvm-0.13.0-gentoo commit in: target-arm/

[Doug Goldstein]

commit:     e485959b33e1abdfa16f05e800de9edaad924b09
Author:     Aurelien Jarno <aurelien <AT> aurel32 <DOT> net>
AuthorDate: Mon Dec 27 18:54:49 2010 +0000
Commit:     Doug Goldstein <cardoe <AT> gentoo <DOT> org>
CommitDate: Fri May 27 18:02:02 2011 +0000
URL:        http://git.overlays.gentoo.org/gitweb/?p=proj/qemu-kvm.git;a=commit;h=e485959b

target-arm: fix bug in translation of REVSH

The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.

Reported-by: Johan Bengtsson <teofrastius <AT> gmail.com>
Signed-off-by: Aurelien Jarno <aurelien <AT> aurel32.net>
(cherry picked from commit 1a855029af40df40144a322bba0e1e61c68eed2a)

Signed-off-by: Aurelien Jarno <aurelien <AT> aurel32.net>

---
 target-arm/translate.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6fcdd7e..cb19dd7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -250,13 +250,9 @@ static void gen_rev16(TCGv var)
 /* Byteswap low halfword and sign extend.  */
 static void gen_revsh(TCGv var)
 {
-    TCGv tmp = new_tmp();
-    tcg_gen_shri_i32(tmp, var, 8);
-    tcg_gen_andi_i32(tmp, tmp, 0x00ff);
-    tcg_gen_shli_i32(var, var, 8);
-    tcg_gen_ext8s_i32(var, var);
-    tcg_gen_or_i32(var, var, tmp);
-    dead_tmp(tmp);
+    tcg_gen_ext16u_i32(var, var);
+    tcg_gen_bswap16_i32(var, var);
+    tcg_gen_ext16s_i32(var, var);
 }
 
 /* Unsigned bitfield extract.  */