From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pigeon.gentoo.org ([208.92.234.80] helo=lists.gentoo.org) by finch.gentoo.org with esmtp (Exim 4.60) (envelope-from ) id 1QbORV-0005iv-TC for garchives@archives.gentoo.org; Tue, 28 Jun 2011 02:54:26 +0000 Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 1436D1C023; Tue, 28 Jun 2011 02:54:17 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by pigeon.gentoo.org (Postfix) with ESMTP id C63AE1C023 for ; Tue, 28 Jun 2011 02:54:16 +0000 (UTC) Received: from pelican.gentoo.org (unknown [66.219.59.40]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id F3A3A1BC01C for ; Tue, 28 Jun 2011 02:54:15 +0000 (UTC) Received: from localhost.localdomain (localhost [127.0.0.1]) by pelican.gentoo.org (Postfix) with ESMTP id 5B83C8003E for ; Tue, 28 Jun 2011 02:54:15 +0000 (UTC) From: "Matt Turner" To: gentoo-commits@lists.gentoo.org Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Matt Turner" Message-ID: Subject: [gentoo-commits] proj/catalyst:master commit in: modules/catalyst/arch/ X-VCS-Repository: proj/catalyst X-VCS-Files: modules/catalyst/arch/mips.py X-VCS-Directories: modules/catalyst/arch/ X-VCS-Committer: mattst88 X-VCS-Committer-Name: Matt Turner X-VCS-Revision: d1c26d0eff8b75e8aa8692e4bc41fc135965ddb6 Date: Tue, 28 Jun 2011 02:54:15 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: quoted-printable X-Archives-Salt: X-Archives-Hash: 81ce7ee05b461fa3701484d92f27d578 commit: d1c26d0eff8b75e8aa8692e4bc41fc135965ddb6 Author: Matt Turner gentoo org> AuthorDate: Tue Jun 28 00:54:25 2011 +0000 Commit: Matt Turner gmail com> CommitDate: Tue Jun 28 00:54:25 2011 +0000 URL: http://git.overlays.gentoo.org/gitweb/?p=3Dproj/catalyst.git;= a=3Dcommit;h=3Dd1c26d0e mips.py: include R4x00 and loongson workarounds in mips3 --- modules/catalyst/arch/mips.py | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/modules/catalyst/arch/mips.py b/modules/catalyst/arch/mips.p= y index 4c4af0c..16ec207 100644 --- a/modules/catalyst/arch/mips.py +++ b/modules/catalyst/arch/mips.py @@ -45,26 +45,26 @@ class arch_mips3(generic_mips): "Builder class for MIPS III [Big-endian]" def __init__(self,myspec): generic_mips.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D32 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D32 -mfix-r4000 -mfix-r44= 00 -pipe" =20 class arch_mips3_n32(generic_mips64): "Builder class for MIPS III [Big-endian N32]" def __init__(self,myspec): generic_mips64.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3Dn32 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3Dn32 -mfix-r4000 -mfix-r4= 400 -pipe" =20 class arch_mips3_n64(generic_mips64): "Builder class for MIPS III [Big-endian N64]" def __init__(self,myspec): generic_mips64.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -mfix-r4000 -mfix-r44= 00 -pipe" =20 class arch_mips3_multilib(generic_mips64,generic_multilib): "Builder class for MIPS III [Big-endian multilib]" def __init__(self,myspec): generic_mips64.__init__(self,myspec) generic_multilib.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mfix-r4000 -mfix-r4400 -pipe" =20 class arch_mips4(generic_mips64): "Builder class for MIPS IV [Big-endian]" @@ -101,26 +101,26 @@ class arch_mipsel3(generic_mipsel): "Builder class for all MIPS III [Little-endian]" def __init__(self,myspec): generic_mipsel.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D32 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D32 -Wa,-mfix-loongson2f-= nop -pipe" =20 class arch_mipsel3_n32(generic_mips64el): "Builder class for all MIPS III [Little-endian N32]" def __init__(self,myspec): generic_mips64el.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3Dn32 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3Dn32 -Wa,-mfix-loongson2f= -nop -pipe" =20 class arch_mipsel3_n64(generic_mips64el): "Builder class for MIPS III [Little-endian N64]" def __init__(self,myspec): generic_mips64el.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -Wa,-mfix-loongson2f-= nop -pipe" =20 class arch_mipsel3_multilib(generic_mips64el,generic_multilib): "Builder class for MIPS III [Little-endian multilib]" def __init__(self,myspec): generic_mips64el.__init__(self,myspec) generic_multilib.__init__(self,myspec) - self.settings["CFLAGS"]=3D"-O2 -mips3 -pipe" + self.settings["CFLAGS"]=3D"-O2 -mips3 -Wa,-mfix-loongson2f-nop -pipe" =20 class arch_loongson2e(generic_mipsel): "Builder class for all Loongson 2E [Little-endian]"