From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pigeon.gentoo.org ([208.92.234.80] helo=lists.gentoo.org) by finch.gentoo.org with esmtp (Exim 4.60) (envelope-from ) id 1QaVgg-0000Cg-DZ for garchives@archives.gentoo.org; Sat, 25 Jun 2011 16:26:27 +0000 Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 0F5161C0D4; Sat, 25 Jun 2011 16:26:08 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by pigeon.gentoo.org (Postfix) with ESMTP id C41EF1C0D4 for ; Sat, 25 Jun 2011 16:26:08 +0000 (UTC) Received: from pelican.gentoo.org (unknown [66.219.59.40]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id 07EF42AC02D for ; Sat, 25 Jun 2011 16:26:08 +0000 (UTC) Received: from localhost.localdomain (localhost [127.0.0.1]) by pelican.gentoo.org (Postfix) with ESMTP id 6E6C280042 for ; Sat, 25 Jun 2011 16:26:07 +0000 (UTC) From: "Matt Turner" To: gentoo-commits@lists.gentoo.org Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Matt Turner" Message-ID: Subject: [gentoo-commits] proj/catalyst:master commit in: /, modules/catalyst/arch/ X-VCS-Repository: proj/catalyst X-VCS-Files: ChangeLog modules/catalyst/arch/mips.py X-VCS-Directories: / modules/catalyst/arch/ X-VCS-Committer: mattst88 X-VCS-Committer-Name: Matt Turner X-VCS-Revision: bd0e09653358771df2ae9782ba9e757671f0c65c Date: Sat, 25 Jun 2011 16:26:07 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: quoted-printable X-Archives-Salt: X-Archives-Hash: 18c1a6144ef5bc3a8cb9f2589abfd819 commit: bd0e09653358771df2ae9782ba9e757671f0c65c Author: Matt Turner gentoo org> AuthorDate: Sat Jun 25 16:16:07 2011 +0000 Commit: Matt Turner gmail com> CommitDate: Sat Jun 25 16:16:07 2011 +0000 URL: http://git.overlays.gentoo.org/gitweb/?p=3Dproj/catalyst.git;= a=3Dcommit;h=3Dbd0e0965 mips.py: add multilib (and missing n64) classes --- ChangeLog | 3 ++ modules/catalyst/arch/mips.py | 53 +++++++++++++++++++++++++++++++++++= ++++++ 2 files changed, 56 insertions(+), 0 deletions(-) diff --git a/ChangeLog b/ChangeLog index 6f98efd..30eb83a 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4,6 +4,9 @@ # $Id$ =20 25 Jun 2011; Matt Turner + modules/catalyst/arch/mips.py: add multilib (and missing n64) classes + + 25 Jun 2011; Matt Turner modules/catalyst/arch/mips.py: remove n32/n64 USE flags =20 25 Jun 2011; Matt Turner diff --git a/modules/catalyst/arch/mips.py b/modules/catalyst/arch/mips.p= y index 51b6812..4c4af0c 100644 --- a/modules/catalyst/arch/mips.py +++ b/modules/catalyst/arch/mips.py @@ -29,6 +29,12 @@ class generic_mips64el(catalyst.arch.generic_arch): self.settings["CHROOT"]=3D"chroot" self.settings["CHOST"]=3D"mips64el-unknown-linux-gnu" =20 +class generic_multilib(catalyst.arch.generic_arch): + "Abstract base class for MIPS multilib" + def __init__(self,myspec): + catalyst.arch.generic_arch.__init__(self,myspec) + self.settings["HOSTUSE"]=3D["multilib"] + class arch_mips1(generic_mips): "Builder class for MIPS I [Big-endian]" def __init__(self,myspec): @@ -53,6 +59,13 @@ class arch_mips3_n64(generic_mips64): generic_mips64.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -pipe" =20 +class arch_mips3_multilib(generic_mips64,generic_multilib): + "Builder class for MIPS III [Big-endian multilib]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips3 -pipe" + class arch_mips4(generic_mips64): "Builder class for MIPS IV [Big-endian]" def __init__(self,myspec): @@ -71,6 +84,13 @@ class arch_mips4_n64(generic_mips64): generic_mips64.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips4 -mabi=3D64 -pipe" =20 +class arch_mips4_multilib(generic_mips64,generic_multilib): + "Builder class for MIPS IV [Big-endian multilib]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips4 -pipe" + class arch_mipsel1(generic_mipsel): "Builder class for all MIPS I [Little-endian]" def __init__(self,myspec): @@ -89,6 +109,19 @@ class arch_mipsel3_n32(generic_mips64el): generic_mips64el.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3Dn32 -pipe" =20 +class arch_mipsel3_n64(generic_mips64el): + "Builder class for MIPS III [Little-endian N64]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips3 -mabi=3D64 -pipe" + +class arch_mipsel3_multilib(generic_mips64el,generic_multilib): + "Builder class for MIPS III [Little-endian multilib]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips3 -pipe" + class arch_loongson2e(generic_mipsel): "Builder class for all Loongson 2E [Little-endian]" def __init__(self,myspec): @@ -125,6 +158,19 @@ class arch_mipsel4_n32(generic_mips64el): generic_mips64el.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips4 -mabi=3Dn32 -pipe" =20 +class arch_mipsel4_n64(generic_mips64el): + "Builder class for MIPS IV [Little-endian N64]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips4 -mabi=3D64 -pipe" + +class arch_mipsel4_multilib(generic_mips64el,generic_multilib): + "Builder class for MIPS IV [Little-endian multilib]" + def __init__(self,myspec): + generic_mips64el.__init__(self,myspec) + generic_multilib.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -mips4 -pipe" + class arch_cobalt(generic_mipsel): "Builder class for all cobalt [Little-endian]" def __init__(self,myspec): @@ -147,14 +193,21 @@ _subarch_map =3D { "mips3" : arch_mips3, "mips3_n32" : arch_mips3_n32, "mips3_n64" : arch_mips3_n64, + "mips3_multilib": arch_mips3_multilib, "mips4" : arch_mips4, "mips4_n32" : arch_mips4_n32, + "mips4_n64" : arch_mips4_n64, + "mips4_multilib": arch_mips4_multilib, "mipsel" : arch_mipsel1, "mipsel1" : arch_mipsel1, "mipsel3" : arch_mipsel3, "mipsel3_n32" : arch_mipsel3_n32, + "mipsel3_n64" : arch_mipsel3_n64, + "mipsel3_multilib" : arch_mipsel3_multilib, "mipsel4" : arch_mipsel4, "mipsel4_n32" : arch_mipsel4_n32, + "mipsel4_n64" : arch_mipsel4_n64, + "mipsel4_multilib" : arch_mipsel4_multilib, "loongson2e" : arch_loongson2e, "loongson2e_n32" : arch_loongson2e_n32, "loongson2f" : arch_loongson2f,