From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pigeon.gentoo.org ([208.92.234.80] helo=lists.gentoo.org) by finch.gentoo.org with esmtp (Exim 4.60) (envelope-from ) id 1QvHMR-000496-Gw for garchives@archives.gentoo.org; Sun, 21 Aug 2011 23:23:23 +0000 Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id CD21721C1B4; Sun, 21 Aug 2011 23:23:15 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by pigeon.gentoo.org (Postfix) with ESMTP id 8FE3E21C1B2 for ; Sun, 21 Aug 2011 23:23:15 +0000 (UTC) Received: from pelican.gentoo.org (unknown [66.219.59.40]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id D22EE1B4006 for ; Sun, 21 Aug 2011 23:23:14 +0000 (UTC) Received: from localhost.localdomain (localhost [127.0.0.1]) by pelican.gentoo.org (Postfix) with ESMTP id 2A7B880043 for ; Sun, 21 Aug 2011 23:23:14 +0000 (UTC) From: "Matt Turner" To: gentoo-commits@lists.gentoo.org Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Matt Turner" Message-ID: Subject: [gentoo-commits] proj/catalyst:master commit in: modules/catalyst/arch/ X-VCS-Repository: proj/catalyst X-VCS-Files: modules/catalyst/arch/mips.py X-VCS-Directories: modules/catalyst/arch/ X-VCS-Committer: mattst88 X-VCS-Committer-Name: Matt Turner X-VCS-Revision: b87c3ba69dc8e3a6b596df7392a0a44ac9745ce0 Date: Sun, 21 Aug 2011 23:23:14 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: quoted-printable X-Archives-Salt: X-Archives-Hash: 6a7eb4ce4edf435b5576419cb4b38ae3 commit: b87c3ba69dc8e3a6b596df7392a0a44ac9745ce0 Author: Matt Turner gmail com> AuthorDate: Sun Aug 21 23:20:16 2011 +0000 Commit: Matt Turner gmail com> CommitDate: Sun Aug 21 23:20:16 2011 +0000 URL: http://git.overlays.gentoo.org/gitweb/?p=3Dproj/catalyst.git;= a=3Dcommit;h=3Db87c3ba6 mips.py: add mips4_r10k classes --- modules/catalyst/arch/mips.py | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-) diff --git a/modules/catalyst/arch/mips.py b/modules/catalyst/arch/mips.p= y index f2fb0c8..9296069 100644 --- a/modules/catalyst/arch/mips.py +++ b/modules/catalyst/arch/mips.py @@ -95,6 +95,30 @@ class arch_mips4_multilib(generic_mips64): generic_mips64.__init__(self,myspec) self.settings["CFLAGS"]=3D"-O2 -mips4 -pipe" =20 +class arch_mips4_r10k(generic_mips): + "Builder class for MIPS IV R10k [Big-endian]" + def __init__(self,myspec): + generic_mips.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dr10k -mabi=3D32 -pipe" + +class arch_mips4_r10k_n32(generic_mips64): + "Builder class for MIPS IV R10k [Big-endian N32]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dr10k -mabi=3Dn32 -pipe" + +class arch_mips4_r10k_n64(generic_mips64): + "Builder class for MIPS IV R10k [Big-endian N64]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dr10k -mabi=3D64 -pipe" + +class arch_mips4_r10k_multilib(generic_mips64): + "Builder class for MIPS IV R10k [Big-endian multilib]" + def __init__(self,myspec): + generic_mips64.__init__(self,myspec) + self.settings["CFLAGS"]=3D"-O2 -march=3Dr10k -pipe" + class arch_mips64(generic_mips): "Builder class for MIPS 64 [Big-endian]" def __init__(self,myspec): @@ -310,6 +334,10 @@ _subarch_map =3D { "mips4_n32" : arch_mips4_n32, "mips4_n64" : arch_mips4_n64, "mips4_multilib": arch_mips4_multilib, + "mips4_r10k" : arch_mips4_r10k, + "mips4_r10k_n32": arch_mips4_r10k_n32, + "mips4_r10k_n64": arch_mips4_r10k_n64, + "mips4_r10k_multilib": arch_mips4_r10k_multilib, "mips64" : arch_mips64, "mips64_n32" : arch_mips64_n32, "mips64_n64" : arch_mips64_n64,