* [gentoo-commits] repo/gentoo:master commit in: dev-util/spirv-headers/, dev-util/spirv-headers/files/
@ 2019-07-22 17:15 Matt Turner
0 siblings, 0 replies; 2+ messages in thread
From: Matt Turner @ 2019-07-22 17:15 UTC (permalink / raw
To: gentoo-commits
commit: 242531335e988f1fc7e82b15267e4da48bb81e09
Author: Matt Turner <mattst88 <AT> gentoo <DOT> org>
AuthorDate: Mon Jul 22 17:06:07 2019 +0000
Commit: Matt Turner <mattst88 <AT> gentoo <DOT> org>
CommitDate: Mon Jul 22 17:15:46 2019 +0000
URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=24253133
dev-util/spirv-headers: Drop old versions
Signed-off-by: Matt Turner <mattst88 <AT> gentoo.org>
| 3 ---
| 25 ----------------------
| 17 ---------------
| 17 ---------------
| 19 ----------------
5 files changed, 81 deletions(-)
--git a/dev-util/spirv-headers/Manifest b/dev-util/spirv-headers/Manifest
index d0fe1f0a491..3c91ba344be 100644
--- a/dev-util/spirv-headers/Manifest
+++ b/dev-util/spirv-headers/Manifest
@@ -1,4 +1 @@
-DIST spirv-headers-1.3.1_pre20180710.tar.gz 281382 BLAKE2B 9e38c7779af97cae27c595f816d1e1cc99eb29e086dd4b6cb76cb4696f73f1e05f92f022b77639f5a80f517df75996fdbd10d7bb11cc6eccad8144a7b8b776d5 SHA512 5f0c174ea07dccefdd10242f5122e10b11f8975d2fb36f77975497050b10841fcb4a7f19d90c9ef5853a81dabc8d93b91621d07175a1cf3ab8ba7f6c16fe51fe
-DIST spirv-headers-1.3.4_pre20180917.tar.gz 283733 BLAKE2B 6bf0f5c00ae827f8a4b560dcbbe4c42d810cebefe0beecd3e7a022dc1f04bc2ed77f03ec2c0d0e6bf141ab1e4f058362f307c672cf92d83a8d1ceac2a200e659 SHA512 1fab471d07c9e85e75a3de08dccdd4ff7296ffd2cb265cb6cf7038e654c9d2afd8a2ee923eacfd2c47e02c5b139ab49271e489ce1b94f719b063be8910274598
DIST spirv-headers-1.3.4_pre20190302.tar.gz 333676 BLAKE2B 7ac46ed9d369164d187564e12438001ebc77c912385b4ef8a5de4ff26942f27ce88486f980b69111e804c6aad5a7f4724913833f0dfd6246bf070dc5023df7df SHA512 d1e6ce59764ad03228cc12fedb1e16fca8c3ab5827882e1f3dec9c3d735125dddbd06fa4955ac3358bec2de8211164511e2d16205f175484e070b2bd87262c51
-DIST spirv-headers-1.3.tar.gz 279415 BLAKE2B 77e36c02d072daa3aff7eceda53a5d6cd060564f494986a9a99c52d833330605e67c6f8ba2968d656b955f188da2c0bea18b11c834d11ed334f5c33eb14b4e9c SHA512 c612c4fcffefc3a277a9713712150c7e6b696eb676737b4968809784ef32c004820d9abd22389082203fc0853a87f920754b7c9b6b43d85131e750d09e267036
diff --git a/dev-util/spirv-headers/files/spirv-headers-Get-rid-of-custom-target.patch b/dev-util/spirv-headers/files/spirv-headers-Get-rid-of-custom-target.patch
deleted file mode 100644
index b1581f5417b..00000000000
--- a/dev-util/spirv-headers/files/spirv-headers-Get-rid-of-custom-target.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From c44560949ec78dd13fe1394bf2957e4fd5adec79 Mon Sep 17 00:00:00 2001
-From: Brian Evans <grknight@gentoo.org>
-Date: Wed, 14 Mar 2018 20:00:22 -0400
-Subject: [PATCH] Get rid of custom target
-
----
- CMakeLists.txt | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index a5bff17..bbc3ddc 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -45,7 +45,5 @@ project(SPIRV-Headers)
- # 3. cmake --build . install-headers
-
- file(GLOB_RECURSE FILES include/spirv/*)
--add_custom_target(install-headers
-- COMMAND cmake -E copy_directory ${CMAKE_CURRENT_SOURCE_DIR}/include/spirv ${CMAKE_INSTALL_PREFIX}/include/spirv)
--
-+INSTALL(DIRECTORY include/spirv/ DESTINATION include/spirv)
- add_subdirectory(example)
---
-2.16.2
-
diff --git a/dev-util/spirv-headers/spirv-headers-1.3.1_pre20180710.ebuild b/dev-util/spirv-headers/spirv-headers-1.3.1_pre20180710.ebuild
deleted file mode 100644
index c3de1e2ba58..00000000000
--- a/dev-util/spirv-headers/spirv-headers-1.3.1_pre20180710.ebuild
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 1999-2018 Gentoo Foundation
-# Distributed under the terms of the GNU General Public License v2
-
-EAPI=6
-
-inherit cmake-utils
-
-DESCRIPTION="Machine-readable files for the SPIR-V Registry"
-HOMEPAGE="https://www.khronos.org/registry/spir-v/"
-EGIT_COMMIT="ff684ffc6a35d2a58f0f63108877d0064ea33feb"
-SRC_URI="https://github.com/KhronosGroup/SPIRV-Headers/archive/${EGIT_COMMIT}.tar.gz -> ${P}.tar.gz"
-
-LICENSE="MIT"
-SLOT="0"
-KEYWORDS="~amd64 ~x86"
-
-S="${WORKDIR}/SPIRV-Headers-${EGIT_COMMIT}"
diff --git a/dev-util/spirv-headers/spirv-headers-1.3.4_pre20180917.ebuild b/dev-util/spirv-headers/spirv-headers-1.3.4_pre20180917.ebuild
deleted file mode 100644
index 72a6122d8ce..00000000000
--- a/dev-util/spirv-headers/spirv-headers-1.3.4_pre20180917.ebuild
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 1999-2019 Gentoo Authors
-# Distributed under the terms of the GNU General Public License v2
-
-EAPI=6
-
-inherit cmake-utils
-
-DESCRIPTION="Machine-readable files for the SPIR-V Registry"
-HOMEPAGE="https://www.khronos.org/registry/spir-v/"
-EGIT_COMMIT="dcf23bdabacc3c54b83b1f9367e7a8adb27f8d87"
-SRC_URI="https://github.com/KhronosGroup/SPIRV-Headers/archive/${EGIT_COMMIT}.tar.gz -> ${P}.tar.gz"
-
-LICENSE="MIT"
-SLOT="0"
-KEYWORDS="amd64 ~x86"
-
-S="${WORKDIR}/SPIRV-Headers-${EGIT_COMMIT}"
diff --git a/dev-util/spirv-headers/spirv-headers-1.3.ebuild b/dev-util/spirv-headers/spirv-headers-1.3.ebuild
deleted file mode 100644
index 4edaed9c09a..00000000000
--- a/dev-util/spirv-headers/spirv-headers-1.3.ebuild
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright 1999-2018 Gentoo Foundation
-# Distributed under the terms of the GNU General Public License v2
-
-EAPI=6
-
-inherit cmake-utils
-
-DESCRIPTION="Machine-readable files for the SPIR-V Registry"
-HOMEPAGE="https://www.khronos.org/registry/spir-v/"
-EGIT_COMMIT="02ffc719aa9f9c1dce5ce05743fb1afe6cbf17ea"
-SRC_URI="https://github.com/KhronosGroup/SPIRV-Headers/archive/${EGIT_COMMIT}.tar.gz -> ${P}.tar.gz"
-
-LICENSE="MIT"
-SLOT="0"
-KEYWORDS="~amd64 ~x86"
-
-PATCHES=( "${FILESDIR}"/${PN}-Get-rid-of-custom-target.patch )
-
-S="${WORKDIR}/SPIRV-Headers-${EGIT_COMMIT}"
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [gentoo-commits] repo/gentoo:master commit in: dev-util/spirv-headers/, dev-util/spirv-headers/files/
@ 2025-03-09 16:42 Conrad Kostecki
0 siblings, 0 replies; 2+ messages in thread
From: Conrad Kostecki @ 2025-03-09 16:42 UTC (permalink / raw
To: gentoo-commits
commit: 1221daf762c4f681a39ca073c61bad38c5b99b2a
Author: Conrad Kostecki <conikost <AT> gentoo <DOT> org>
AuthorDate: Sun Mar 9 16:41:18 2025 +0000
Commit: Conrad Kostecki <conikost <AT> gentoo <DOT> org>
CommitDate: Sun Mar 9 16:42:52 2025 +0000
URL: https://gitweb.gentoo.org/repo/gentoo.git/commit/?id=1221daf7
dev-util/spirv-headers: move patches to devspace
Signed-off-by: Conrad Kostecki <conikost <AT> gentoo.org>
| 1 +
| 499 ------------
| 842 ---------------------
| 14 +-
4 files changed, 10 insertions(+), 1346 deletions(-)
--git a/dev-util/spirv-headers/Manifest b/dev-util/spirv-headers/Manifest
index 8bc0a2a5fc01..0c0b0afb1c53 100644
--- a/dev-util/spirv-headers/Manifest
+++ b/dev-util/spirv-headers/Manifest
@@ -1 +1,2 @@
+DIST spirv-headers-1.4.304.0-new-intel-headers.tar.xz 6024 BLAKE2B 6a92f50022d311c0f45447fc9f435e93850eaee1b5ff9f6698c9c521160926dcd194f597b46ffd03027c21d5b0dd842b61a4a0b40a4cd2a27ad4cae7b64954a9 SHA512 1ce11b443852b272a9bbfd08c9802c2f6087ce54e5f3166445bafbdfc549d1cd7a03f91aa3cbd3bf556cc0dc0ae774d365a4b24fb9a7aab30497dd82983186b1
DIST spirv-headers-1.4.304.0.tar.gz 532015 BLAKE2B c2b4fcc61c4d6c6134c19ddd31722fd2a87820621ce46fd8f5c810c53b0d671b40d4c5b2cef7ec54e273b17518778ea6059f5ff7f06049799457b8c4586a73ef SHA512 09d6a2e4f7758e8e6bd0c5036d8895befc96ea049b655d2786df4092a6f4ad4185a70ca83bd38683afb9b5e1ec45d8699a38d19774ca39c09f4f199fa1085946
diff --git a/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-spv_intel_2d_block_io-header.patch b/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-spv_intel_2d_block_io-header.patch
deleted file mode 100644
index 7eba292b3ff3..000000000000
--- a/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-spv_intel_2d_block_io-header.patch
+++ /dev/null
@@ -1,499 +0,0 @@
-From 9ca0e67b5e5b5879ac75d498aa6c5d81a7bece35 Mon Sep 17 00:00:00 2001
-From: Ben Ashbaugh <ben.ashbaugh@intel.com>
-Date: Wed, 15 Jan 2025 08:34:48 -0800
-Subject: [PATCH] grammar and header changes for SPV_INTEL_2d_block_io (#470)
-
----
- include/spirv/unified1/spirv.bf | 8 ++
- .../spirv/unified1/spirv.core.grammar.json | 120 +++++++++++++++++-
- include/spirv/unified1/spirv.cs | 8 ++
- include/spirv/unified1/spirv.h | 21 +++
- include/spirv/unified1/spirv.hpp | 21 +++
- include/spirv/unified1/spirv.hpp11 | 21 +++
- include/spirv/unified1/spirv.json | 8 ++
- include/spirv/unified1/spirv.lua | 8 ++
- include/spirv/unified1/spirv.py | 8 ++
- include/spirv/unified1/spv.d | 8 ++
- 10 files changed, 228 insertions(+), 3 deletions(-)
-
-diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
-index 4f067ddb3..e71dc7a82 100644
---- a/include/spirv/unified1/spirv.bf
-+++ b/include/spirv/unified1/spirv.bf
-@@ -1284,6 +1284,9 @@ namespace Spv
- GlobalVariableHostAccessINTEL = 6187,
- GlobalVariableFPGADecorationsINTEL = 6189,
- SubgroupBufferPrefetchINTEL = 6220,
-+ Subgroup2DBlockIOINTEL = 6228,
-+ Subgroup2DBlockTransformINTEL = 6229,
-+ Subgroup2DBlockTransposeINTEL = 6230,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -2305,6 +2308,11 @@ namespace Spv
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
-index b4ec4dc11..6afa5c430 100644
---- a/include/spirv/unified1/spirv.core.grammar.json
-+++ b/include/spirv/unified1/spirv.core.grammar.json
-@@ -10130,6 +10130,100 @@
- "capabilities" : [ "SubgroupBufferPrefetchINTEL" ],
- "version" : "None"
- },
-+ {
-+ "opname" : "OpSubgroup2DBlockLoadINTEL",
-+ "class" : "Group",
-+ "opcode" : 6231,
-+ "operands" : [
-+ { "kind" : "IdRef", "name" : "'Element Size'" },
-+ { "kind" : "IdRef", "name" : "'Block Width'" },
-+ { "kind" : "IdRef", "name" : "'Block Height'" },
-+ { "kind" : "IdRef", "name" : "'Block Count'" },
-+ { "kind" : "IdRef", "name" : "'Src Base Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Memory Width'" },
-+ { "kind" : "IdRef", "name" : "'Memory Height'" },
-+ { "kind" : "IdRef", "name" : "'Memory Pitch'" },
-+ { "kind" : "IdRef", "name" : "'Coordinate'" },
-+ { "kind" : "IdRef", "name" : "'Dst Pointer'" }
-+ ],
-+ "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
-+ "version" : "None"
-+ },
-+ {
-+ "opname" : "OpSubgroup2DBlockLoadTransformINTEL",
-+ "class" : "Group",
-+ "opcode" : 6232,
-+ "operands" : [
-+ { "kind" : "IdRef", "name" : "'Element Size'" },
-+ { "kind" : "IdRef", "name" : "'Block Width'" },
-+ { "kind" : "IdRef", "name" : "'Block Height'" },
-+ { "kind" : "IdRef", "name" : "'Block Count'" },
-+ { "kind" : "IdRef", "name" : "'Src Base Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Memory Width'" },
-+ { "kind" : "IdRef", "name" : "'Memory Height'" },
-+ { "kind" : "IdRef", "name" : "'Memory Pitch'" },
-+ { "kind" : "IdRef", "name" : "'Coordinate'" },
-+ { "kind" : "IdRef", "name" : "'Dst Pointer'" }
-+ ],
-+ "capabilities" : [ "Subgroup2DBlockTransformINTEL" ],
-+ "version" : "None"
-+ },
-+ {
-+ "opname" : "OpSubgroup2DBlockLoadTransposeINTEL",
-+ "class" : "Group",
-+ "opcode" : 6233,
-+ "operands" : [
-+ { "kind" : "IdRef", "name" : "'Element Size'" },
-+ { "kind" : "IdRef", "name" : "'Block Width'" },
-+ { "kind" : "IdRef", "name" : "'Block Height'" },
-+ { "kind" : "IdRef", "name" : "'Block Count'" },
-+ { "kind" : "IdRef", "name" : "'Src Base Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Memory Width'" },
-+ { "kind" : "IdRef", "name" : "'Memory Height'" },
-+ { "kind" : "IdRef", "name" : "'Memory Pitch'" },
-+ { "kind" : "IdRef", "name" : "'Coordinate'" },
-+ { "kind" : "IdRef", "name" : "'Dst Pointer'" }
-+ ],
-+ "capabilities" : [ "Subgroup2DBlockTransposeINTEL" ],
-+ "version" : "None"
-+ },
-+ {
-+ "opname" : "OpSubgroup2DBlockPrefetchINTEL",
-+ "class" : "Group",
-+ "opcode" : 6234,
-+ "operands" : [
-+ { "kind" : "IdRef", "name" : "'Element Size'" },
-+ { "kind" : "IdRef", "name" : "'Block Width'" },
-+ { "kind" : "IdRef", "name" : "'Block Height'" },
-+ { "kind" : "IdRef", "name" : "'Block Count'" },
-+ { "kind" : "IdRef", "name" : "'Src Base Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Memory Width'" },
-+ { "kind" : "IdRef", "name" : "'Memory Height'" },
-+ { "kind" : "IdRef", "name" : "'Memory Pitch'" },
-+ { "kind" : "IdRef", "name" : "'Coordinate'" }
-+ ],
-+ "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
-+ "version" : "None"
-+ },
-+ {
-+ "opname" : "OpSubgroup2DBlockStoreINTEL",
-+ "class" : "Group",
-+ "opcode" : 6235,
-+ "operands" : [
-+ { "kind" : "IdRef", "name" : "'Element Size'" },
-+ { "kind" : "IdRef", "name" : "'Block Width'" },
-+ { "kind" : "IdRef", "name" : "'Block Height'" },
-+ { "kind" : "IdRef", "name" : "'Block Count'" },
-+ { "kind" : "IdRef", "name" : "'Src Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Dst Base Pointer'" },
-+ { "kind" : "IdRef", "name" : "'Memory Width'" },
-+ { "kind" : "IdRef", "name" : "'Memory Height'" },
-+ { "kind" : "IdRef", "name" : "'Memory Pitch'" },
-+ { "kind" : "IdRef", "name" : "'Coordinate'" }
-+ ],
-+ "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
-+ "version" : "None"
-+ },
- {
- "opname" : "OpGroupIMulKHR",
- "class" : "Group",
-@@ -16587,6 +16681,26 @@
- "extensions": [ "SPV_INTEL_subgroup_buffer_prefetch" ],
- "version" : "None"
- },
-+ {
-+ "enumerant" : "Subgroup2DBlockIOINTEL",
-+ "value" : 6228,
-+ "extensions": [ "SPV_INTEL_2d_block_io" ],
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "Subgroup2DBlockTransformINTEL",
-+ "value" : 6229,
-+ "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
-+ "extensions": [ "SPV_INTEL_2d_block_io" ],
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "Subgroup2DBlockTransposeINTEL",
-+ "value" : 6230,
-+ "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
-+ "extensions": [ "SPV_INTEL_2d_block_io" ],
-+ "version" : "None"
-+ },
- {
- "enumerant" : "GroupUniformArithmeticKHR",
- "value" : 6400,
-@@ -16595,9 +16709,9 @@
- },
- {
- "enumerant" : "MaskedGatherScatterINTEL",
-- "value" : 6427,
-- "extensions" : [ "SPV_INTEL_masked_gather_scatter"],
-- "version" : "None"
-+ "value" : 6427,
-+ "extensions" : [ "SPV_INTEL_masked_gather_scatter"],
-+ "version" : "None"
- },
- {
- "enumerant" : "CacheControlsINTEL",
-diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
-index c01cf947f..7a995ace2 100644
---- a/include/spirv/unified1/spirv.cs
-+++ b/include/spirv/unified1/spirv.cs
-@@ -1283,6 +1283,9 @@ public enum Capability
- GlobalVariableHostAccessINTEL = 6187,
- GlobalVariableFPGADecorationsINTEL = 6189,
- SubgroupBufferPrefetchINTEL = 6220,
-+ Subgroup2DBlockIOINTEL = 6228,
-+ Subgroup2DBlockTransformINTEL = 6229,
-+ Subgroup2DBlockTransposeINTEL = 6230,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -2304,6 +2307,11 @@ public enum Op
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
-index 0b16b37d0..66631b9a2 100644
---- a/include/spirv/unified1/spirv.h
-+++ b/include/spirv/unified1/spirv.h
-@@ -1254,6 +1254,9 @@ typedef enum SpvCapability_ {
- SpvCapabilityGlobalVariableHostAccessINTEL = 6187,
- SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6189,
- SpvCapabilitySubgroupBufferPrefetchINTEL = 6220,
-+ SpvCapabilitySubgroup2DBlockIOINTEL = 6228,
-+ SpvCapabilitySubgroup2DBlockTransformINTEL = 6229,
-+ SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230,
- SpvCapabilityGroupUniformArithmeticKHR = 6400,
- SpvCapabilityMaskedGatherScatterINTEL = 6427,
- SpvCapabilityCacheControlsINTEL = 6441,
-@@ -2245,6 +2248,11 @@ typedef enum SpvOp_ {
- SpvOpControlBarrierWaitINTEL = 6143,
- SpvOpArithmeticFenceEXT = 6145,
- SpvOpSubgroupBlockPrefetchINTEL = 6221,
-+ SpvOpSubgroup2DBlockLoadINTEL = 6231,
-+ SpvOpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ SpvOpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ SpvOpSubgroup2DBlockPrefetchINTEL = 6234,
-+ SpvOpSubgroup2DBlockStoreINTEL = 6235,
- SpvOpGroupIMulKHR = 6401,
- SpvOpGroupFMulKHR = 6402,
- SpvOpGroupBitwiseAndKHR = 6403,
-@@ -3015,6 +3023,11 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
- case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
- case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
- case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
- case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3946,6 +3959,9 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
- case SpvCapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
- case SpvCapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
- case SpvCapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
-+ case SpvCapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
-+ case SpvCapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
-+ case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
- case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case SpvCapabilityCacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4859,6 +4875,11 @@ inline const char* SpvOpToString(SpvOp value) {
- case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
- case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
- case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
-+ case SpvOpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
-+ case SpvOpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
-+ case SpvOpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
-+ case SpvOpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
-+ case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
- case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
- case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
- case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
-index fc6b9f7a1..16486dd38 100644
---- a/include/spirv/unified1/spirv.hpp
-+++ b/include/spirv/unified1/spirv.hpp
-@@ -1250,6 +1250,9 @@ enum Capability {
- CapabilityGlobalVariableHostAccessINTEL = 6187,
- CapabilityGlobalVariableFPGADecorationsINTEL = 6189,
- CapabilitySubgroupBufferPrefetchINTEL = 6220,
-+ CapabilitySubgroup2DBlockIOINTEL = 6228,
-+ CapabilitySubgroup2DBlockTransformINTEL = 6229,
-+ CapabilitySubgroup2DBlockTransposeINTEL = 6230,
- CapabilityGroupUniformArithmeticKHR = 6400,
- CapabilityMaskedGatherScatterINTEL = 6427,
- CapabilityCacheControlsINTEL = 6441,
-@@ -2241,6 +2244,11 @@ enum Op {
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-@@ -3011,6 +3019,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
- case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
- case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
- case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
- case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3942,6 +3955,9 @@ inline const char* CapabilityToString(Capability value) {
- case CapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
- case CapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
- case CapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
-+ case CapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
-+ case CapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
-+ case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
- case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case CapabilityCacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4855,6 +4871,11 @@ inline const char* OpToString(Op value) {
- case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
- case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
- case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
-+ case OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
-+ case OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
-+ case OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
-+ case OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
-+ case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
- case OpGroupIMulKHR: return "OpGroupIMulKHR";
- case OpGroupFMulKHR: return "OpGroupFMulKHR";
- case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
-index b79fab5f6..d7181f390 100644
---- a/include/spirv/unified1/spirv.hpp11
-+++ b/include/spirv/unified1/spirv.hpp11
-@@ -1250,6 +1250,9 @@ enum class Capability : unsigned {
- GlobalVariableHostAccessINTEL = 6187,
- GlobalVariableFPGADecorationsINTEL = 6189,
- SubgroupBufferPrefetchINTEL = 6220,
-+ Subgroup2DBlockIOINTEL = 6228,
-+ Subgroup2DBlockTransformINTEL = 6229,
-+ Subgroup2DBlockTransposeINTEL = 6230,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -2241,6 +2244,11 @@ enum class Op : unsigned {
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-@@ -3011,6 +3019,11 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
- case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
- case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
- case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroup2DBlockLoadINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroup2DBlockLoadTransformINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
- case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3942,6 +3955,9 @@ inline const char* CapabilityToString(Capability value) {
- case Capability::GlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
- case Capability::GlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
- case Capability::SubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
-+ case Capability::Subgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
-+ case Capability::Subgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
-+ case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
- case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case Capability::CacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4855,6 +4871,11 @@ inline const char* OpToString(Op value) {
- case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
- case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
- case Op::OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
-+ case Op::OpSubgroup2DBlockLoadINTEL: return "OpSubgroup2DBlockLoadINTEL";
-+ case Op::OpSubgroup2DBlockLoadTransformINTEL: return "OpSubgroup2DBlockLoadTransformINTEL";
-+ case Op::OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
-+ case Op::OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
-+ case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
- case Op::OpGroupIMulKHR: return "OpGroupIMulKHR";
- case Op::OpGroupFMulKHR: return "OpGroupFMulKHR";
- case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
-index e9cbf74a9..31d490e00 100644
---- a/include/spirv/unified1/spirv.json
-+++ b/include/spirv/unified1/spirv.json
-@@ -1226,6 +1226,9 @@
- "GlobalVariableHostAccessINTEL": 6187,
- "GlobalVariableFPGADecorationsINTEL": 6189,
- "SubgroupBufferPrefetchINTEL": 6220,
-+ "Subgroup2DBlockIOINTEL": 6228,
-+ "Subgroup2DBlockTransformINTEL": 6229,
-+ "Subgroup2DBlockTransposeINTEL": 6230,
- "GroupUniformArithmeticKHR": 6400,
- "MaskedGatherScatterINTEL": 6427,
- "CacheControlsINTEL": 6441,
-@@ -2238,6 +2241,11 @@
- "OpControlBarrierWaitINTEL": 6143,
- "OpArithmeticFenceEXT": 6145,
- "OpSubgroupBlockPrefetchINTEL": 6221,
-+ "OpSubgroup2DBlockLoadINTEL": 6231,
-+ "OpSubgroup2DBlockLoadTransformINTEL": 6232,
-+ "OpSubgroup2DBlockLoadTransposeINTEL": 6233,
-+ "OpSubgroup2DBlockPrefetchINTEL": 6234,
-+ "OpSubgroup2DBlockStoreINTEL": 6235,
- "OpGroupIMulKHR": 6401,
- "OpGroupFMulKHR": 6402,
- "OpGroupBitwiseAndKHR": 6403,
-diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
-index 855608c83..ef74edda9 100644
---- a/include/spirv/unified1/spirv.lua
-+++ b/include/spirv/unified1/spirv.lua
-@@ -1241,6 +1241,9 @@ spv = {
- GlobalVariableHostAccessINTEL = 6187,
- GlobalVariableFPGADecorationsINTEL = 6189,
- SubgroupBufferPrefetchINTEL = 6220,
-+ Subgroup2DBlockIOINTEL = 6228,
-+ Subgroup2DBlockTransformINTEL = 6229,
-+ Subgroup2DBlockTransposeINTEL = 6230,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -2232,6 +2235,11 @@ spv = {
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
-index 44f2a58df..21a54691b 100644
---- a/include/spirv/unified1/spirv.py
-+++ b/include/spirv/unified1/spirv.py
-@@ -1212,6 +1212,9 @@
- 'GlobalVariableHostAccessINTEL' : 6187,
- 'GlobalVariableFPGADecorationsINTEL' : 6189,
- 'SubgroupBufferPrefetchINTEL' : 6220,
-+ 'Subgroup2DBlockIOINTEL' : 6228,
-+ 'Subgroup2DBlockTransformINTEL' : 6229,
-+ 'Subgroup2DBlockTransposeINTEL' : 6230,
- 'GroupUniformArithmeticKHR' : 6400,
- 'MaskedGatherScatterINTEL' : 6427,
- 'CacheControlsINTEL' : 6441,
-@@ -2179,6 +2182,11 @@
- 'OpControlBarrierWaitINTEL' : 6143,
- 'OpArithmeticFenceEXT' : 6145,
- 'OpSubgroupBlockPrefetchINTEL' : 6221,
-+ 'OpSubgroup2DBlockLoadINTEL' : 6231,
-+ 'OpSubgroup2DBlockLoadTransformINTEL' : 6232,
-+ 'OpSubgroup2DBlockLoadTransposeINTEL' : 6233,
-+ 'OpSubgroup2DBlockPrefetchINTEL' : 6234,
-+ 'OpSubgroup2DBlockStoreINTEL' : 6235,
- 'OpGroupIMulKHR' : 6401,
- 'OpGroupFMulKHR' : 6402,
- 'OpGroupBitwiseAndKHR' : 6403,
-diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
-index 73e72c911..68770c93e 100644
---- a/include/spirv/unified1/spv.d
-+++ b/include/spirv/unified1/spv.d
-@@ -1286,6 +1286,9 @@ enum Capability : uint
- GlobalVariableHostAccessINTEL = 6187,
- GlobalVariableFPGADecorationsINTEL = 6189,
- SubgroupBufferPrefetchINTEL = 6220,
-+ Subgroup2DBlockIOINTEL = 6228,
-+ Subgroup2DBlockTransformINTEL = 6229,
-+ Subgroup2DBlockTransposeINTEL = 6230,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -2307,6 +2310,11 @@ enum Op : uint
- OpControlBarrierWaitINTEL = 6143,
- OpArithmeticFenceEXT = 6145,
- OpSubgroupBlockPrefetchINTEL = 6221,
-+ OpSubgroup2DBlockLoadINTEL = 6231,
-+ OpSubgroup2DBlockLoadTransformINTEL = 6232,
-+ OpSubgroup2DBlockLoadTransposeINTEL = 6233,
-+ OpSubgroup2DBlockPrefetchINTEL = 6234,
-+ OpSubgroup2DBlockStoreINTEL = 6235,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
diff --git a/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-subgroupmatrixmultiplyaccumulateintel-header.patch b/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-subgroupmatrixmultiplyaccumulateintel-header.patch
deleted file mode 100644
index 6fa524139176..000000000000
--- a/dev-util/spirv-headers/files/spirv-headers-1.4.304.0-add-subgroupmatrixmultiplyaccumulateintel-header.patch
+++ /dev/null
@@ -1,842 +0,0 @@
-From 2b2e05e088841c63c0b6fd4c9fb380d8688738d3 Mon Sep 17 00:00:00 2001
-From: Ben Ashbaugh <ben.ashbaugh@intel.com>
-Date: Thu, 16 Jan 2025 07:34:23 -0800
-Subject: [PATCH] grammar and header changes for
- SPV_INTEL_subgroup_matrix_multiply_accumulate (#471)
-
----
- include/spirv/unified1/spirv.bf | 40 +++++++
- .../spirv/unified1/spirv.core.grammar.json | 103 ++++++++++++++++++
- include/spirv/unified1/spirv.cs | 40 +++++++
- include/spirv/unified1/spirv.h | 41 +++++++
- include/spirv/unified1/spirv.hpp | 45 ++++++++
- include/spirv/unified1/spirv.hpp11 | 45 ++++++++
- include/spirv/unified1/spirv.json | 23 ++++
- include/spirv/unified1/spirv.lua | 38 +++++++
- include/spirv/unified1/spirv.py | 37 +++++++
- include/spirv/unified1/spv.d | 40 +++++++
- tools/buildHeaders/jsonToSpirv.cpp | 5 +
- tools/buildHeaders/jsonToSpirv.h | 1 +
- 12 files changed, 458 insertions(+)
-
-diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
-index 1f8f466b1..d5cb80b3f 100644
---- a/include/spirv/unified1/spirv.bf
-+++ b/include/spirv/unified1/spirv.bf
-@@ -1288,6 +1288,7 @@ namespace Spv
- Subgroup2DBlockIOINTEL = 6228,
- Subgroup2DBlockTransformINTEL = 6229,
- Subgroup2DBlockTransposeINTEL = 6230,
-+ SubgroupMatrixMultiplyAccumulateINTEL = 6236,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -1528,6 +1529,44 @@ namespace Spv
- Max = 0x7fffffff,
- }
-
-+ [AllowDuplicates, CRepr] public enum MatrixMultiplyAccumulateOperandsShift
-+ {
-+ MatrixASignedComponentsINTEL = 0,
-+ MatrixBSignedComponentsINTEL = 1,
-+ MatrixCBFloat16INTEL = 2,
-+ MatrixResultBFloat16INTEL = 3,
-+ MatrixAPackedInt8INTEL = 4,
-+ MatrixBPackedInt8INTEL = 5,
-+ MatrixAPackedInt4INTEL = 6,
-+ MatrixBPackedInt4INTEL = 7,
-+ MatrixATF32INTEL = 8,
-+ MatrixBTF32INTEL = 9,
-+ MatrixAPackedFloat16INTEL = 10,
-+ MatrixBPackedFloat16INTEL = 11,
-+ MatrixAPackedBFloat16INTEL = 12,
-+ MatrixBPackedBFloat16INTEL = 13,
-+ Max = 0x7fffffff,
-+ }
-+
-+ [AllowDuplicates, CRepr] public enum MatrixMultiplyAccumulateOperandsMask
-+ {
-+ MaskNone = 0,
-+ MatrixASignedComponentsINTEL = 0x00000001,
-+ MatrixBSignedComponentsINTEL = 0x00000002,
-+ MatrixCBFloat16INTEL = 0x00000004,
-+ MatrixResultBFloat16INTEL = 0x00000008,
-+ MatrixAPackedInt8INTEL = 0x00000010,
-+ MatrixBPackedInt8INTEL = 0x00000020,
-+ MatrixAPackedInt4INTEL = 0x00000040,
-+ MatrixBPackedInt4INTEL = 0x00000080,
-+ MatrixATF32INTEL = 0x00000100,
-+ MatrixBTF32INTEL = 0x00000200,
-+ MatrixAPackedFloat16INTEL = 0x00000400,
-+ MatrixBPackedFloat16INTEL = 0x00000800,
-+ MatrixAPackedBFloat16INTEL = 0x00001000,
-+ MatrixBPackedBFloat16INTEL = 0x00002000,
-+ }
-+
- [AllowDuplicates, CRepr] public enum RawAccessChainOperandsShift
- {
- RobustnessPerComponentNV = 0,
-@@ -2314,6 +2353,7 @@ namespace Spv
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
-index d09c155a1..a6c4f288e 100644
---- a/include/spirv/unified1/spirv.core.grammar.json
-+++ b/include/spirv/unified1/spirv.core.grammar.json
-@@ -10224,6 +10224,22 @@
- "capabilities" : [ "Subgroup2DBlockIOINTEL" ],
- "version" : "None"
- },
-+ {
-+ "opname" : "OpSubgroupMatrixMultiplyAccumulateINTEL",
-+ "class" : "Group",
-+ "opcode" : 6237,
-+ "operands" : [
-+ { "kind" : "IdResultType" },
-+ { "kind" : "IdResult" },
-+ { "kind" : "IdRef", "name" : "'K Dim'" },
-+ { "kind" : "IdRef", "name" : "'Matrix A'" },
-+ { "kind" : "IdRef", "name" : "'Matrix B'" },
-+ { "kind" : "IdRef", "name" : "'Matrix C'" },
-+ { "kind" : "MatrixMultiplyAccumulateOperands", "quantifier" : "?" }
-+ ],
-+ "capabilities" : [ "SubgroupMatrixMultiplyAccumulateINTEL" ],
-+ "version" : "None"
-+ },
- {
- "opname" : "OpGroupIMulKHR",
- "class" : "Group",
-@@ -16706,6 +16722,12 @@
- "extensions": [ "SPV_INTEL_2d_block_io" ],
- "version" : "None"
- },
-+ {
-+ "enumerant" : "SubgroupMatrixMultiplyAccumulateINTEL",
-+ "value" : 6236,
-+ "extensions": [ "SPV_INTEL_subgroup_matrix_multiply_accumulate" ],
-+ "version" : "None"
-+ },
- {
- "enumerant" : "GroupUniformArithmeticKHR",
- "value" : 6400,
-@@ -17065,6 +17087,87 @@
- }
- ]
- },
-+ {
-+ "category" : "BitEnum",
-+ "kind" : "MatrixMultiplyAccumulateOperands",
-+ "enumerants" : [
-+ {
-+ "enumerant" : "None",
-+ "value" : "0x0",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixASignedComponentsINTEL",
-+ "value" : "0x1",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBSignedComponentsINTEL",
-+ "value" : "0x2",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixCBFloat16INTEL",
-+ "value" : "0x4",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixResultBFloat16INTEL",
-+ "value" : "0x8",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixAPackedInt8INTEL",
-+ "value" : "0x10",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBPackedInt8INTEL",
-+ "value" : "0x20",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixAPackedInt4INTEL",
-+ "value" : "0x40",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBPackedInt4INTEL",
-+ "value" : "0x80",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixATF32INTEL",
-+ "value" : "0x100",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBTF32INTEL",
-+ "value" : "0x200",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixAPackedFloat16INTEL",
-+ "value" : "0x400",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBPackedFloat16INTEL",
-+ "value" : "0x800",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixAPackedBFloat16INTEL",
-+ "value" : "0x1000",
-+ "version" : "None"
-+ },
-+ {
-+ "enumerant" : "MatrixBPackedBFloat16INTEL",
-+ "value" : "0x2000",
-+ "version" : "None"
-+ }
-+ ]
-+ },
- {
- "category" : "ValueEnum",
- "kind" : "FPEncoding",
-diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
-index 57773d65d..80fe0d36a 100644
---- a/include/spirv/unified1/spirv.cs
-+++ b/include/spirv/unified1/spirv.cs
-@@ -1287,6 +1287,7 @@ public enum Capability
- Subgroup2DBlockIOINTEL = 6228,
- Subgroup2DBlockTransformINTEL = 6229,
- Subgroup2DBlockTransposeINTEL = 6230,
-+ SubgroupMatrixMultiplyAccumulateINTEL = 6236,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -1527,6 +1528,44 @@ public enum NamedMaximumNumberOfRegisters
- Max = 0x7fffffff,
- }
-
-+ public enum MatrixMultiplyAccumulateOperandsShift
-+ {
-+ MatrixASignedComponentsINTEL = 0,
-+ MatrixBSignedComponentsINTEL = 1,
-+ MatrixCBFloat16INTEL = 2,
-+ MatrixResultBFloat16INTEL = 3,
-+ MatrixAPackedInt8INTEL = 4,
-+ MatrixBPackedInt8INTEL = 5,
-+ MatrixAPackedInt4INTEL = 6,
-+ MatrixBPackedInt4INTEL = 7,
-+ MatrixATF32INTEL = 8,
-+ MatrixBTF32INTEL = 9,
-+ MatrixAPackedFloat16INTEL = 10,
-+ MatrixBPackedFloat16INTEL = 11,
-+ MatrixAPackedBFloat16INTEL = 12,
-+ MatrixBPackedBFloat16INTEL = 13,
-+ Max = 0x7fffffff,
-+ }
-+
-+ public enum MatrixMultiplyAccumulateOperandsMask
-+ {
-+ MaskNone = 0,
-+ MatrixASignedComponentsINTEL = 0x00000001,
-+ MatrixBSignedComponentsINTEL = 0x00000002,
-+ MatrixCBFloat16INTEL = 0x00000004,
-+ MatrixResultBFloat16INTEL = 0x00000008,
-+ MatrixAPackedInt8INTEL = 0x00000010,
-+ MatrixBPackedInt8INTEL = 0x00000020,
-+ MatrixAPackedInt4INTEL = 0x00000040,
-+ MatrixBPackedInt4INTEL = 0x00000080,
-+ MatrixATF32INTEL = 0x00000100,
-+ MatrixBTF32INTEL = 0x00000200,
-+ MatrixAPackedFloat16INTEL = 0x00000400,
-+ MatrixBPackedFloat16INTEL = 0x00000800,
-+ MatrixAPackedBFloat16INTEL = 0x00001000,
-+ MatrixBPackedBFloat16INTEL = 0x00002000,
-+ }
-+
- public enum RawAccessChainOperandsShift
- {
- RobustnessPerComponentNV = 0,
-@@ -2313,6 +2352,7 @@ public enum Op
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
-index 72b5e434b..6a91aa9b7 100644
---- a/include/spirv/unified1/spirv.h
-+++ b/include/spirv/unified1/spirv.h
-@@ -1258,6 +1258,7 @@ typedef enum SpvCapability_ {
- SpvCapabilitySubgroup2DBlockIOINTEL = 6228,
- SpvCapabilitySubgroup2DBlockTransformINTEL = 6229,
- SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230,
-+ SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236,
- SpvCapabilityGroupUniformArithmeticKHR = 6400,
- SpvCapabilityMaskedGatherScatterINTEL = 6427,
- SpvCapabilityCacheControlsINTEL = 6441,
-@@ -1472,6 +1473,42 @@ typedef enum SpvNamedMaximumNumberOfRegisters_ {
- SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff,
- } SpvNamedMaximumNumberOfRegisters;
-
-+typedef enum SpvMatrixMultiplyAccumulateOperandsShift_ {
-+ SpvMatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELShift = 0,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELShift = 1,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELShift = 2,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELShift = 3,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELShift = 4,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELShift = 5,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELShift = 6,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELShift = 7,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixATF32INTELShift = 8,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBTF32INTELShift = 9,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELShift = 10,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELShift = 11,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELShift = 12,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELShift = 13,
-+ SpvMatrixMultiplyAccumulateOperandsMax = 0x7fffffff,
-+} SpvMatrixMultiplyAccumulateOperandsShift;
-+
-+typedef enum SpvMatrixMultiplyAccumulateOperandsMask_ {
-+ SpvMatrixMultiplyAccumulateOperandsMaskNone = 0,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELMask = 0x00000001,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELMask = 0x00000002,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELMask = 0x00000004,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELMask = 0x00000008,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELMask = 0x00000010,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELMask = 0x00000020,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELMask = 0x00000040,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELMask = 0x00000080,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixATF32INTELMask = 0x00000100,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBTF32INTELMask = 0x00000200,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELMask = 0x00000400,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELMask = 0x00000800,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELMask = 0x00001000,
-+ SpvMatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELMask = 0x00002000,
-+} SpvMatrixMultiplyAccumulateOperandsMask;
-+
- typedef enum SpvRawAccessChainOperandsShift_ {
- SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0,
- SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1,
-@@ -2254,6 +2291,7 @@ typedef enum SpvOp_ {
- SpvOpSubgroup2DBlockLoadTransposeINTEL = 6233,
- SpvOpSubgroup2DBlockPrefetchINTEL = 6234,
- SpvOpSubgroup2DBlockStoreINTEL = 6235,
-+ SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- SpvOpGroupIMulKHR = 6401,
- SpvOpGroupFMulKHR = 6402,
- SpvOpGroupBitwiseAndKHR = 6403,
-@@ -3029,6 +3067,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
- case SpvOpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
- case SpvOpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
- case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
-+ case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
- case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3964,6 +4003,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
- case SpvCapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
- case SpvCapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
- case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
-+ case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
- case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case SpvCapabilityCacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4882,6 +4922,7 @@ inline const char* SpvOpToString(SpvOp value) {
- case SpvOpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
- case SpvOpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
- case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
-+ case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
- case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
- case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
- case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
-index ffc5102fc..619226360 100644
---- a/include/spirv/unified1/spirv.hpp
-+++ b/include/spirv/unified1/spirv.hpp
-@@ -1254,6 +1254,7 @@ enum Capability {
- CapabilitySubgroup2DBlockIOINTEL = 6228,
- CapabilitySubgroup2DBlockTransformINTEL = 6229,
- CapabilitySubgroup2DBlockTransposeINTEL = 6230,
-+ CapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236,
- CapabilityGroupUniformArithmeticKHR = 6400,
- CapabilityMaskedGatherScatterINTEL = 6427,
- CapabilityCacheControlsINTEL = 6441,
-@@ -1468,6 +1469,42 @@ enum NamedMaximumNumberOfRegisters {
- NamedMaximumNumberOfRegistersMax = 0x7fffffff,
- };
-
-+enum MatrixMultiplyAccumulateOperandsShift {
-+ MatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELShift = 0,
-+ MatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELShift = 1,
-+ MatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELShift = 2,
-+ MatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELShift = 3,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELShift = 4,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELShift = 5,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELShift = 6,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELShift = 7,
-+ MatrixMultiplyAccumulateOperandsMatrixATF32INTELShift = 8,
-+ MatrixMultiplyAccumulateOperandsMatrixBTF32INTELShift = 9,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELShift = 10,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELShift = 11,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELShift = 12,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELShift = 13,
-+ MatrixMultiplyAccumulateOperandsMax = 0x7fffffff,
-+};
-+
-+enum MatrixMultiplyAccumulateOperandsMask {
-+ MatrixMultiplyAccumulateOperandsMaskNone = 0,
-+ MatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELMask = 0x00000001,
-+ MatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELMask = 0x00000002,
-+ MatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELMask = 0x00000004,
-+ MatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELMask = 0x00000008,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELMask = 0x00000010,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELMask = 0x00000020,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELMask = 0x00000040,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELMask = 0x00000080,
-+ MatrixMultiplyAccumulateOperandsMatrixATF32INTELMask = 0x00000100,
-+ MatrixMultiplyAccumulateOperandsMatrixBTF32INTELMask = 0x00000200,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELMask = 0x00000400,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELMask = 0x00000800,
-+ MatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELMask = 0x00001000,
-+ MatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELMask = 0x00002000,
-+};
-+
- enum RawAccessChainOperandsShift {
- RawAccessChainOperandsRobustnessPerComponentNVShift = 0,
- RawAccessChainOperandsRobustnessPerElementNVShift = 1,
-@@ -2250,6 +2287,7 @@ enum Op {
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-@@ -3025,6 +3063,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
- case OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
- case OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
- case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
-+ case OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
- case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3960,6 +3999,7 @@ inline const char* CapabilityToString(Capability value) {
- case CapabilitySubgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
- case CapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
- case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
-+ case CapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
- case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case CapabilityCacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4878,6 +4918,7 @@ inline const char* OpToString(Op value) {
- case OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
- case OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
- case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
-+ case OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
- case OpGroupIMulKHR: return "OpGroupIMulKHR";
- case OpGroupFMulKHR: return "OpGroupFMulKHR";
- case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-@@ -4948,6 +4989,10 @@ inline TensorAddressingOperandsMask operator|(TensorAddressingOperandsMask a, Te
- inline TensorAddressingOperandsMask operator&(TensorAddressingOperandsMask a, TensorAddressingOperandsMask b) { return TensorAddressingOperandsMask(unsigned(a) & unsigned(b)); }
- inline TensorAddressingOperandsMask operator^(TensorAddressingOperandsMask a, TensorAddressingOperandsMask b) { return TensorAddressingOperandsMask(unsigned(a) ^ unsigned(b)); }
- inline TensorAddressingOperandsMask operator~(TensorAddressingOperandsMask a) { return TensorAddressingOperandsMask(~unsigned(a)); }
-+inline MatrixMultiplyAccumulateOperandsMask operator|(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) | unsigned(b)); }
-+inline MatrixMultiplyAccumulateOperandsMask operator&(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) & unsigned(b)); }
-+inline MatrixMultiplyAccumulateOperandsMask operator^(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) ^ unsigned(b)); }
-+inline MatrixMultiplyAccumulateOperandsMask operator~(MatrixMultiplyAccumulateOperandsMask a) { return MatrixMultiplyAccumulateOperandsMask(~unsigned(a)); }
- inline RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); }
- inline RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); }
- inline RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); }
-diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
-index 0fa3a005e..22a7c43e0 100644
---- a/include/spirv/unified1/spirv.hpp11
-+++ b/include/spirv/unified1/spirv.hpp11
-@@ -1254,6 +1254,7 @@ enum class Capability : unsigned {
- Subgroup2DBlockIOINTEL = 6228,
- Subgroup2DBlockTransformINTEL = 6229,
- Subgroup2DBlockTransposeINTEL = 6230,
-+ SubgroupMatrixMultiplyAccumulateINTEL = 6236,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -1468,6 +1469,42 @@ enum class NamedMaximumNumberOfRegisters : unsigned {
- Max = 0x7fffffff,
- };
-
-+enum class MatrixMultiplyAccumulateOperandsShift : unsigned {
-+ MatrixASignedComponentsINTEL = 0,
-+ MatrixBSignedComponentsINTEL = 1,
-+ MatrixCBFloat16INTEL = 2,
-+ MatrixResultBFloat16INTEL = 3,
-+ MatrixAPackedInt8INTEL = 4,
-+ MatrixBPackedInt8INTEL = 5,
-+ MatrixAPackedInt4INTEL = 6,
-+ MatrixBPackedInt4INTEL = 7,
-+ MatrixATF32INTEL = 8,
-+ MatrixBTF32INTEL = 9,
-+ MatrixAPackedFloat16INTEL = 10,
-+ MatrixBPackedFloat16INTEL = 11,
-+ MatrixAPackedBFloat16INTEL = 12,
-+ MatrixBPackedBFloat16INTEL = 13,
-+ Max = 0x7fffffff,
-+};
-+
-+enum class MatrixMultiplyAccumulateOperandsMask : unsigned {
-+ MaskNone = 0,
-+ MatrixASignedComponentsINTEL = 0x00000001,
-+ MatrixBSignedComponentsINTEL = 0x00000002,
-+ MatrixCBFloat16INTEL = 0x00000004,
-+ MatrixResultBFloat16INTEL = 0x00000008,
-+ MatrixAPackedInt8INTEL = 0x00000010,
-+ MatrixBPackedInt8INTEL = 0x00000020,
-+ MatrixAPackedInt4INTEL = 0x00000040,
-+ MatrixBPackedInt4INTEL = 0x00000080,
-+ MatrixATF32INTEL = 0x00000100,
-+ MatrixBTF32INTEL = 0x00000200,
-+ MatrixAPackedFloat16INTEL = 0x00000400,
-+ MatrixBPackedFloat16INTEL = 0x00000800,
-+ MatrixAPackedBFloat16INTEL = 0x00001000,
-+ MatrixBPackedBFloat16INTEL = 0x00002000,
-+};
-+
- enum class RawAccessChainOperandsShift : unsigned {
- RobustnessPerComponentNV = 0,
- RobustnessPerElementNV = 1,
-@@ -2250,6 +2287,7 @@ enum class Op : unsigned {
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-@@ -3025,6 +3063,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
- case Op::OpSubgroup2DBlockLoadTransposeINTEL: *hasResult = false; *hasResultType = false; break;
- case Op::OpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
- case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
-+ case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
- case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
- case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
- case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
-@@ -3960,6 +3999,7 @@ inline const char* CapabilityToString(Capability value) {
- case Capability::Subgroup2DBlockIOINTEL: return "Subgroup2DBlockIOINTEL";
- case Capability::Subgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL";
- case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
-+ case Capability::SubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
- case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
- case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
- case Capability::CacheControlsINTEL: return "CacheControlsINTEL";
-@@ -4878,6 +4918,7 @@ inline const char* OpToString(Op value) {
- case Op::OpSubgroup2DBlockLoadTransposeINTEL: return "OpSubgroup2DBlockLoadTransposeINTEL";
- case Op::OpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL";
- case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
-+ case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
- case Op::OpGroupIMulKHR: return "OpGroupIMulKHR";
- case Op::OpGroupFMulKHR: return "OpGroupFMulKHR";
- case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
-@@ -4948,6 +4989,10 @@ constexpr TensorAddressingOperandsMask operator|(TensorAddressingOperandsMask a,
- constexpr TensorAddressingOperandsMask operator&(TensorAddressingOperandsMask a, TensorAddressingOperandsMask b) { return TensorAddressingOperandsMask(unsigned(a) & unsigned(b)); }
- constexpr TensorAddressingOperandsMask operator^(TensorAddressingOperandsMask a, TensorAddressingOperandsMask b) { return TensorAddressingOperandsMask(unsigned(a) ^ unsigned(b)); }
- constexpr TensorAddressingOperandsMask operator~(TensorAddressingOperandsMask a) { return TensorAddressingOperandsMask(~unsigned(a)); }
-+constexpr MatrixMultiplyAccumulateOperandsMask operator|(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) | unsigned(b)); }
-+constexpr MatrixMultiplyAccumulateOperandsMask operator&(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) & unsigned(b)); }
-+constexpr MatrixMultiplyAccumulateOperandsMask operator^(MatrixMultiplyAccumulateOperandsMask a, MatrixMultiplyAccumulateOperandsMask b) { return MatrixMultiplyAccumulateOperandsMask(unsigned(a) ^ unsigned(b)); }
-+constexpr MatrixMultiplyAccumulateOperandsMask operator~(MatrixMultiplyAccumulateOperandsMask a) { return MatrixMultiplyAccumulateOperandsMask(~unsigned(a)); }
- constexpr RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); }
- constexpr RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); }
- constexpr RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); }
-diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
-index 28ecbed91..3e2757f2e 100644
---- a/include/spirv/unified1/spirv.json
-+++ b/include/spirv/unified1/spirv.json
-@@ -1230,6 +1230,7 @@
- "Subgroup2DBlockIOINTEL": 6228,
- "Subgroup2DBlockTransformINTEL": 6229,
- "Subgroup2DBlockTransposeINTEL": 6230,
-+ "SubgroupMatrixMultiplyAccumulateINTEL": 6236,
- "GroupUniformArithmeticKHR": 6400,
- "MaskedGatherScatterINTEL": 6427,
- "CacheControlsINTEL": 6441,
-@@ -1461,6 +1462,27 @@
- "AutoINTEL": 0
- }
- },
-+ {
-+ "Name": "MatrixMultiplyAccumulateOperands",
-+ "Type": "Bit",
-+ "Values":
-+ {
-+ "MatrixASignedComponentsINTEL": 0,
-+ "MatrixBSignedComponentsINTEL": 1,
-+ "MatrixCBFloat16INTEL": 2,
-+ "MatrixResultBFloat16INTEL": 3,
-+ "MatrixAPackedInt8INTEL": 4,
-+ "MatrixBPackedInt8INTEL": 5,
-+ "MatrixAPackedInt4INTEL": 6,
-+ "MatrixBPackedInt4INTEL": 7,
-+ "MatrixATF32INTEL": 8,
-+ "MatrixBTF32INTEL": 9,
-+ "MatrixAPackedFloat16INTEL": 10,
-+ "MatrixBPackedFloat16INTEL": 11,
-+ "MatrixAPackedBFloat16INTEL": 12,
-+ "MatrixBPackedBFloat16INTEL": 13
-+ }
-+ },
- {
- "Name": "RawAccessChainOperands",
- "Type": "Bit",
-@@ -2247,6 +2269,7 @@
- "OpSubgroup2DBlockLoadTransposeINTEL": 6233,
- "OpSubgroup2DBlockPrefetchINTEL": 6234,
- "OpSubgroup2DBlockStoreINTEL": 6235,
-+ "OpSubgroupMatrixMultiplyAccumulateINTEL": 6237,
- "OpGroupIMulKHR": 6401,
- "OpGroupFMulKHR": 6402,
- "OpGroupBitwiseAndKHR": 6403,
-diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
-index 15ffb9086..552a51e20 100644
---- a/include/spirv/unified1/spirv.lua
-+++ b/include/spirv/unified1/spirv.lua
-@@ -1245,6 +1245,7 @@ spv = {
- Subgroup2DBlockIOINTEL = 6228,
- Subgroup2DBlockTransformINTEL = 6229,
- Subgroup2DBlockTransposeINTEL = 6230,
-+ SubgroupMatrixMultiplyAccumulateINTEL = 6236,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -1459,6 +1460,42 @@ spv = {
- Max = 0x7fffffff,
- },
-
-+ MatrixMultiplyAccumulateOperandsShift = {
-+ MatrixASignedComponentsINTEL = 0,
-+ MatrixBSignedComponentsINTEL = 1,
-+ MatrixCBFloat16INTEL = 2,
-+ MatrixResultBFloat16INTEL = 3,
-+ MatrixAPackedInt8INTEL = 4,
-+ MatrixBPackedInt8INTEL = 5,
-+ MatrixAPackedInt4INTEL = 6,
-+ MatrixBPackedInt4INTEL = 7,
-+ MatrixATF32INTEL = 8,
-+ MatrixBTF32INTEL = 9,
-+ MatrixAPackedFloat16INTEL = 10,
-+ MatrixBPackedFloat16INTEL = 11,
-+ MatrixAPackedBFloat16INTEL = 12,
-+ MatrixBPackedBFloat16INTEL = 13,
-+ Max = 0x7fffffff,
-+ },
-+
-+ MatrixMultiplyAccumulateOperandsMask = {
-+ MaskNone = 0,
-+ MatrixASignedComponentsINTEL = 0x00000001,
-+ MatrixBSignedComponentsINTEL = 0x00000002,
-+ MatrixCBFloat16INTEL = 0x00000004,
-+ MatrixResultBFloat16INTEL = 0x00000008,
-+ MatrixAPackedInt8INTEL = 0x00000010,
-+ MatrixBPackedInt8INTEL = 0x00000020,
-+ MatrixAPackedInt4INTEL = 0x00000040,
-+ MatrixBPackedInt4INTEL = 0x00000080,
-+ MatrixATF32INTEL = 0x00000100,
-+ MatrixBTF32INTEL = 0x00000200,
-+ MatrixAPackedFloat16INTEL = 0x00000400,
-+ MatrixBPackedFloat16INTEL = 0x00000800,
-+ MatrixAPackedBFloat16INTEL = 0x00001000,
-+ MatrixBPackedBFloat16INTEL = 0x00002000,
-+ },
-+
- RawAccessChainOperandsShift = {
- RobustnessPerComponentNV = 0,
- RobustnessPerElementNV = 1,
-@@ -2241,6 +2278,7 @@ spv = {
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
-index 1bee93453..57fb9a5ad 100644
---- a/include/spirv/unified1/spirv.py
-+++ b/include/spirv/unified1/spirv.py
-@@ -1216,6 +1216,7 @@
- 'Subgroup2DBlockIOINTEL' : 6228,
- 'Subgroup2DBlockTransformINTEL' : 6229,
- 'Subgroup2DBlockTransposeINTEL' : 6230,
-+ 'SubgroupMatrixMultiplyAccumulateINTEL' : 6236,
- 'GroupUniformArithmeticKHR' : 6400,
- 'MaskedGatherScatterINTEL' : 6427,
- 'CacheControlsINTEL' : 6441,
-@@ -1408,6 +1409,41 @@
- 'AutoINTEL' : 0,
- },
-
-+ 'MatrixMultiplyAccumulateOperandsShift' : {
-+ 'MatrixASignedComponentsINTEL' : 0,
-+ 'MatrixBSignedComponentsINTEL' : 1,
-+ 'MatrixCBFloat16INTEL' : 2,
-+ 'MatrixResultBFloat16INTEL' : 3,
-+ 'MatrixAPackedInt8INTEL' : 4,
-+ 'MatrixBPackedInt8INTEL' : 5,
-+ 'MatrixAPackedInt4INTEL' : 6,
-+ 'MatrixBPackedInt4INTEL' : 7,
-+ 'MatrixATF32INTEL' : 8,
-+ 'MatrixBTF32INTEL' : 9,
-+ 'MatrixAPackedFloat16INTEL' : 10,
-+ 'MatrixBPackedFloat16INTEL' : 11,
-+ 'MatrixAPackedBFloat16INTEL' : 12,
-+ 'MatrixBPackedBFloat16INTEL' : 13,
-+ },
-+
-+ 'MatrixMultiplyAccumulateOperandsMask' : {
-+ 'MaskNone' : 0,
-+ 'MatrixASignedComponentsINTEL' : 0x00000001,
-+ 'MatrixBSignedComponentsINTEL' : 0x00000002,
-+ 'MatrixCBFloat16INTEL' : 0x00000004,
-+ 'MatrixResultBFloat16INTEL' : 0x00000008,
-+ 'MatrixAPackedInt8INTEL' : 0x00000010,
-+ 'MatrixBPackedInt8INTEL' : 0x00000020,
-+ 'MatrixAPackedInt4INTEL' : 0x00000040,
-+ 'MatrixBPackedInt4INTEL' : 0x00000080,
-+ 'MatrixATF32INTEL' : 0x00000100,
-+ 'MatrixBTF32INTEL' : 0x00000200,
-+ 'MatrixAPackedFloat16INTEL' : 0x00000400,
-+ 'MatrixBPackedFloat16INTEL' : 0x00000800,
-+ 'MatrixAPackedBFloat16INTEL' : 0x00001000,
-+ 'MatrixBPackedBFloat16INTEL' : 0x00002000,
-+ },
-+
- 'RawAccessChainOperandsShift' : {
- 'RobustnessPerComponentNV' : 0,
- 'RobustnessPerElementNV' : 1,
-@@ -2188,6 +2224,7 @@
- 'OpSubgroup2DBlockLoadTransposeINTEL' : 6233,
- 'OpSubgroup2DBlockPrefetchINTEL' : 6234,
- 'OpSubgroup2DBlockStoreINTEL' : 6235,
-+ 'OpSubgroupMatrixMultiplyAccumulateINTEL' : 6237,
- 'OpGroupIMulKHR' : 6401,
- 'OpGroupFMulKHR' : 6402,
- 'OpGroupBitwiseAndKHR' : 6403,
-diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
-index 7b31c8e18..2987795f9 100644
---- a/include/spirv/unified1/spv.d
-+++ b/include/spirv/unified1/spv.d
-@@ -1290,6 +1290,7 @@ enum Capability : uint
- Subgroup2DBlockIOINTEL = 6228,
- Subgroup2DBlockTransformINTEL = 6229,
- Subgroup2DBlockTransposeINTEL = 6230,
-+ SubgroupMatrixMultiplyAccumulateINTEL = 6236,
- GroupUniformArithmeticKHR = 6400,
- MaskedGatherScatterINTEL = 6427,
- CacheControlsINTEL = 6441,
-@@ -1530,6 +1531,44 @@ enum NamedMaximumNumberOfRegisters : uint
- Max = 0x7fffffff,
- }
-
-+enum MatrixMultiplyAccumulateOperandsShift : uint
-+{
-+ MatrixASignedComponentsINTEL = 0,
-+ MatrixBSignedComponentsINTEL = 1,
-+ MatrixCBFloat16INTEL = 2,
-+ MatrixResultBFloat16INTEL = 3,
-+ MatrixAPackedInt8INTEL = 4,
-+ MatrixBPackedInt8INTEL = 5,
-+ MatrixAPackedInt4INTEL = 6,
-+ MatrixBPackedInt4INTEL = 7,
-+ MatrixATF32INTEL = 8,
-+ MatrixBTF32INTEL = 9,
-+ MatrixAPackedFloat16INTEL = 10,
-+ MatrixBPackedFloat16INTEL = 11,
-+ MatrixAPackedBFloat16INTEL = 12,
-+ MatrixBPackedBFloat16INTEL = 13,
-+ Max = 0x7fffffff,
-+}
-+
-+enum MatrixMultiplyAccumulateOperandsMask : uint
-+{
-+ MaskNone = 0,
-+ MatrixASignedComponentsINTEL = 0x00000001,
-+ MatrixBSignedComponentsINTEL = 0x00000002,
-+ MatrixCBFloat16INTEL = 0x00000004,
-+ MatrixResultBFloat16INTEL = 0x00000008,
-+ MatrixAPackedInt8INTEL = 0x00000010,
-+ MatrixBPackedInt8INTEL = 0x00000020,
-+ MatrixAPackedInt4INTEL = 0x00000040,
-+ MatrixBPackedInt4INTEL = 0x00000080,
-+ MatrixATF32INTEL = 0x00000100,
-+ MatrixBTF32INTEL = 0x00000200,
-+ MatrixAPackedFloat16INTEL = 0x00000400,
-+ MatrixBPackedFloat16INTEL = 0x00000800,
-+ MatrixAPackedBFloat16INTEL = 0x00001000,
-+ MatrixBPackedBFloat16INTEL = 0x00002000,
-+}
-+
- enum RawAccessChainOperandsShift : uint
- {
- RobustnessPerComponentNV = 0,
-@@ -2316,6 +2355,7 @@ enum Op : uint
- OpSubgroup2DBlockLoadTransposeINTEL = 6233,
- OpSubgroup2DBlockPrefetchINTEL = 6234,
- OpSubgroup2DBlockStoreINTEL = 6235,
-+ OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
- OpGroupIMulKHR = 6401,
- OpGroupFMulKHR = 6402,
- OpGroupBitwiseAndKHR = 6403,
-diff --git a/tools/buildHeaders/jsonToSpirv.cpp b/tools/buildHeaders/jsonToSpirv.cpp
-index ddc299da6..e112ec8b4 100644
---- a/tools/buildHeaders/jsonToSpirv.cpp
-+++ b/tools/buildHeaders/jsonToSpirv.cpp
-@@ -274,6 +274,7 @@ EnumValues HostAccessQualifierParams;
- EnumValues LoadCacheControlParams;
- EnumValues StoreCacheControlParams;
- EnumValues NamedMaximumNumberOfRegistersParams;
-+EnumValues MatrixMultiplyAccumulateOperandsParams;
- EnumValues RawAccessChainOperandsParams;
- EnumValues FPEncodingParams;
-
-@@ -446,6 +447,8 @@ ClassOptionality ToOperandClassAndOptionality(const std::string& operandKind, co
- type = OperandStoreCacheControl;
- } else if (operandKind == "NamedMaximumNumberOfRegisters") {
- type = OperandNamedMaximumNumberOfRegisters;
-+ } else if (operandKind == "MatrixMultiplyAccumulateOperands") {
-+ type = OperandMatrixMultiplyAccumulateOperands;
- } else if (operandKind == "RawAccessChainOperands") {
- type = OperandRawAccessChainOperands;
- } else if (operandKind == "FPEncoding") {
-@@ -836,6 +839,8 @@ void jsonToSpirv(const std::string& jsonPath, bool buildingHeaders)
- establishOperandClass(enumName, OperandStoreCacheControl, &StoreCacheControlParams, operandEnum, category);
- } else if (enumName == "NamedMaximumNumberOfRegisters") {
- establishOperandClass(enumName, OperandNamedMaximumNumberOfRegisters, &NamedMaximumNumberOfRegistersParams, operandEnum, category);
-+ } else if (enumName == "MatrixMultiplyAccumulateOperands") {
-+ establishOperandClass(enumName, OperandMatrixMultiplyAccumulateOperands, &MatrixMultiplyAccumulateOperandsParams, operandEnum, category);
- } else if (enumName == "RawAccessChainOperands") {
- establishOperandClass(enumName, OperandRawAccessChainOperands, &RawAccessChainOperandsParams, operandEnum, category);
- } else if (enumName == "FPEncoding") {
-diff --git a/tools/buildHeaders/jsonToSpirv.h b/tools/buildHeaders/jsonToSpirv.h
-index 9ad34138b..5393220ee 100644
---- a/tools/buildHeaders/jsonToSpirv.h
-+++ b/tools/buildHeaders/jsonToSpirv.h
-@@ -107,6 +107,7 @@ enum OperandClass {
- OperandLoadCacheControl,
- OperandStoreCacheControl,
- OperandNamedMaximumNumberOfRegisters,
-+ OperandMatrixMultiplyAccumulateOperands,
- OperandRawAccessChainOperands,
- OperandFPEncoding,
-
--git a/dev-util/spirv-headers/spirv-headers-1.4.304.0-r1.ebuild b/dev-util/spirv-headers/spirv-headers-1.4.304.0-r1.ebuild
index 92af614f40d6..bbe7eb2d1fcd 100644
--- a/dev-util/spirv-headers/spirv-headers-1.4.304.0-r1.ebuild
+++ b/dev-util/spirv-headers/spirv-headers-1.4.304.0-r1.ebuild
@@ -10,7 +10,10 @@ if [[ ${PV} == *9999* ]]; then
EGIT_REPO_URI="https://github.com/KhronosGroup/${MY_PN}.git"
inherit git-r3
else
- SRC_URI="https://github.com/KhronosGroup/${MY_PN}/archive/vulkan-sdk-${PV}.tar.gz -> ${P}.tar.gz"
+ SRC_URI="
+ https://github.com/KhronosGroup/${MY_PN}/archive/vulkan-sdk-${PV}.tar.gz -> ${P}.tar.gz
+ https://dev.gentoo.org/~conikost/distfiles/${P}-new-intel-headers.tar.xz
+ "
KEYWORDS="amd64 arm arm64 ~loong ppc ppc64 ~riscv ~sparc x86"
S="${WORKDIR}"/${MY_PN}-vulkan-sdk-${PV}
fi
@@ -21,10 +24,11 @@ HOMEPAGE="https://registry.khronos.org/SPIR-V/ https://github.com/KhronosGroup/S
LICENSE="MIT"
SLOT="0"
-PATCHES=(
- "${FILESDIR}/${PN}-1.4.304.0-add-spv_intel_2d_block_io-header.patch"
- "${FILESDIR}/${PN}-1.4.304.0-add-subgroupmatrixmultiplyaccumulateintel-header.patch"
-)
+src_prepare() {
+ cmake_src_prepare
+ eapply "${WORKDIR}/${PN}-1.4.304.0-add-spv_intel_2d_block_io-header.patch"
+ eapply "${WORKDIR}/${PN}-1.4.304.0-add-subgroupmatrixmultiplyaccumulateintel-header.patch"
+}
src_configure() {
local mycmakeargs=(
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2019-07-22 17:15 Matt Turner
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