From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gentoo.org (pigeon.gentoo.org [208.92.234.80]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by finch.gentoo.org (Postfix) with ESMTPS id 0C316158042 for ; Thu, 17 Oct 2024 23:33:40 +0000 (UTC) Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 58125E0973; Thu, 17 Oct 2024 23:33:39 +0000 (UTC) Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by pigeon.gentoo.org (Postfix) with ESMTPS id 3C68BE0973 for ; Thu, 17 Oct 2024 23:33:39 +0000 (UTC) Received: from oystercatcher.gentoo.org (oystercatcher.gentoo.org [148.251.78.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id 434EA341465 for ; Thu, 17 Oct 2024 23:33:38 +0000 (UTC) Received: from localhost.localdomain (localhost [IPv6:::1]) by oystercatcher.gentoo.org (Postfix) with ESMTP id 7F6E1EA0 for ; Thu, 17 Oct 2024 23:33:36 +0000 (UTC) From: "Sam James" To: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: 8bit Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Sam James" Message-ID: <1729207997.137934d3c0119acebb59614f6627e8b4fe299feb.sam@gentoo> Subject: [gentoo-commits] proj/gcc-patches:master commit in: 15.0.0/gentoo/ X-VCS-Repository: proj/gcc-patches X-VCS-Files: 15.0.0/gentoo/72_all_PR117192-andn.patch X-VCS-Directories: 15.0.0/gentoo/ X-VCS-Committer: sam X-VCS-Committer-Name: Sam James X-VCS-Revision: 137934d3c0119acebb59614f6627e8b4fe299feb X-VCS-Branch: master Date: Thu, 17 Oct 2024 23:33:36 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Archives-Salt: bc6b341f-a109-4978-9163-4e93e69b7ea0 X-Archives-Hash: a3db7d1b8c130d504135752e73367a2b commit: 137934d3c0119acebb59614f6627e8b4fe299feb Author: Sam James gentoo org> AuthorDate: Thu Oct 17 23:33:01 2024 +0000 Commit: Sam James gentoo org> CommitDate: Thu Oct 17 23:33:17 2024 +0000 URL: https://gitweb.gentoo.org/proj/gcc-patches.git/commit/?id=137934d3 15.0.0: fix 72_all_PR117192-andn.patch Doh. Apply the patch, not the commit it's fixing... Fixes: e1ed90a71415a98a6d4c7d6efe03b5e0551fbb4c Signed-off-by: Sam James gentoo.org> 15.0.0/gentoo/72_all_PR117192-andn.patch | 98 ++++---------------------------- 1 file changed, 12 insertions(+), 86 deletions(-) diff --git a/15.0.0/gentoo/72_all_PR117192-andn.patch b/15.0.0/gentoo/72_all_PR117192-andn.patch index 5593ae0..f7706c1 100644 --- a/15.0.0/gentoo/72_all_PR117192-andn.patch +++ b/15.0.0/gentoo/72_all_PR117192-andn.patch @@ -1,94 +1,20 @@ https://gcc.gnu.org/PR17192 - -From 70f59d2a1c51bde085d8fc7df002918851e76c9c Mon Sep 17 00:00:00 2001 -From: "Cui, Lili" -Date: Thu, 17 Oct 2024 08:50:38 +0800 -Subject: [PATCH] Support andn_optab for x86 - -Add new andn pattern to match the new optab added by -r15-1890-gf379596e0ba99d. Only enable 64bit, 128bit and -256bit vector ANDN, X86-64 has mask mov instruction when -avx512 is enabled. - -gcc/ChangeLog: - - * config/i386/sse.md (andn3): New. - * config/i386/mmx.md (andn3): New. - -gcc/testsuite/ChangeLog: - - * g++.target/i386/vect-cmp.C: New test. ---- - gcc/config/i386/mmx.md | 7 +++++++ - gcc/config/i386/sse.md | 7 +++++++ - gcc/testsuite/g++.target/i386/vect-cmp.C | 23 +++++++++++++++++++++++ - 3 files changed, 37 insertions(+) - create mode 100644 gcc/testsuite/g++.target/i386/vect-cmp.C +https://gcc.gnu.org/bugzilla/attachment.cgi?id=59373 diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md -index 9d2a82c598e5..ef4ed8b501a1 100644 +index ef4ed8b501a..506f4cab6a8 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md -@@ -4467,6 +4467,13 @@ - operands[0] = lowpart_subreg (V16QImode, operands[0], mode); - }) +@@ -4470,9 +4470,9 @@ (define_split + (define_expand "andn3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (and:MMXMODEI +- (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand")) +- (match_operand:MMXMODEI 2 "register_operand")))] +- "TARGET_SSE2") ++ (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand")) ++ (match_operand:MMXMODEI 1 "register_operand")))] ++ "TARGET_MMX_WITH_SSE") -+(define_expand "andn3" -+ [(set (match_operand:MMXMODEI 0 "register_operand") -+ (and:MMXMODEI -+ (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand")) -+ (match_operand:MMXMODEI 2 "register_operand")))] -+ "TARGET_SSE2") -+ (define_insn "mmx_andnot3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v") - (and:MMXMODEI -diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md -index a45b50ad7324..7be313346677 100644 ---- a/gcc/config/i386/sse.md -+++ b/gcc/config/i386/sse.md -@@ -18438,6 +18438,13 @@ - (match_operand:VI_AVX2 2 "vector_operand")))] - "TARGET_SSE2") - -+(define_expand "andn3" -+ [(set (match_operand:VI 0 "register_operand") -+ (and:VI -+ (not:VI (match_operand:VI 2 "register_operand")) -+ (match_operand:VI 1 "register_operand")))] -+ "TARGET_SSE2") -+ - (define_expand "_andnot3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL -diff --git a/gcc/testsuite/g++.target/i386/vect-cmp.C b/gcc/testsuite/g++.target/i386/vect-cmp.C -new file mode 100644 -index 000000000000..c154474fa51c ---- /dev/null -+++ b/gcc/testsuite/g++.target/i386/vect-cmp.C -@@ -0,0 +1,23 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -march=x86-64-v3 -fdump-tree-optimized" } */ -+ -+#define vect8 __attribute__((vector_size(8) )) -+#define vect16 __attribute__((vector_size(16) )) -+#define vect32 __attribute__((vector_size(32) )) -+ -+vect8 int bar0 (vect8 float a, vect8 float b, vect8 int c) -+{ -+ return (a > b) ? 0 : c; -+} -+ -+vect16 int bar1 (vect16 float a, vect16 float b, vect16 int c) -+{ -+ return (a > b) ? 0 : c; -+} -+ -+vect32 int bar2 (vect32 float a, vect32 float b, vect32 int c) -+{ -+ return (a > b) ? 0 : c; -+} -+ -+/* { dg-final { scan-tree-dump-times ".BIT_ANDN " 3 "optimized" { target { ! ia32 } } } } */ --- -2.43.5