[gentoo-commits] repo/proj/guru:dev commit in: sci-electronics/circt/

["Yuhang Zeng" <unlsycn@unlsycn.com>]

commit:     fe47557fbada13a64eacab72846fd49a0530959f
Author:     Yuhang Zeng <unlsycn <AT> unlsycn <DOT> com>
AuthorDate: Wed Jun 12 16:29:47 2024 +0000
Commit:     Yuhang Zeng <unlsycn <AT> unlsycn <DOT> com>
CommitDate: Wed Jun 12 16:33:10 2024 +0000
URL:        https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=fe47557f

sci-electronics/circt: enable py3.12 and disable py3.10

Signed-off-by: Yuhang Zeng <unlsycn <AT> unlsycn.com>

 sci-electronics/circt/circt-1.14.0.ebuild | 2 +-
 sci-electronics/circt/circt-1.37.0.ebuild | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sci-electronics/circt/circt-1.14.0.ebuild b/sci-electronics/circt/circt-1.14.0.ebuild
index 181b5b44f..42854ef96 100644
--- a/sci-electronics/circt/circt-1.14.0.ebuild
+++ b/sci-electronics/circt/circt-1.14.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
 MY_PV="${PV//./\/}"
 MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995"
 CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{10..11} )
+PYTHON_COMPAT=( python3_{11..12} )
 inherit cmake python-r1
 
 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"

diff --git a/sci-electronics/circt/circt-1.37.0.ebuild b/sci-electronics/circt/circt-1.37.0.ebuild
index ce9f7c46b..0b1a877e5 100644
--- a/sci-electronics/circt/circt-1.37.0.ebuild
+++ b/sci-electronics/circt/circt-1.37.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
 MY_PV="${PV//./\/}"
 MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d"
 CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{10..11} )
+PYTHON_COMPAT=( python3_{11..12} )
 inherit cmake python-r1
 
 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"