From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gentoo.org (pigeon.gentoo.org [208.92.234.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by finch.gentoo.org (Postfix) with ESMTPS id 4AC3A1382C5 for ; Tue, 12 May 2020 09:01:58 +0000 (UTC) Received: from pigeon.gentoo.org (localhost [127.0.0.1]) by pigeon.gentoo.org (Postfix) with SMTP id 23566E086B; Tue, 12 May 2020 09:01:57 +0000 (UTC) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by pigeon.gentoo.org (Postfix) with ESMTPS id 0AB12E086B for ; Tue, 12 May 2020 09:01:57 +0000 (UTC) Received: from oystercatcher.gentoo.org (unknown [IPv6:2a01:4f8:202:4333:225:90ff:fed9:fc84]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id 795D034FFF2 for ; Tue, 12 May 2020 09:01:55 +0000 (UTC) Received: from localhost.localdomain (localhost [IPv6:::1]) by oystercatcher.gentoo.org (Postfix) with ESMTP id 9A23A206 for ; Tue, 12 May 2020 09:01:53 +0000 (UTC) From: "Andrew Ammerlaan" To: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: 8bit Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Andrew Ammerlaan" Message-ID: <1589255786.cec003e759481c0070e3e366b33bb8504aeb046d.andrewammerlaan@gentoo> Subject: [gentoo-commits] repo/proj/guru:master commit in: sci-electronics/verilator/ X-VCS-Repository: repo/proj/guru X-VCS-Files: sci-electronics/verilator/Manifest sci-electronics/verilator/verilator-4.034.ebuild X-VCS-Directories: sci-electronics/verilator/ X-VCS-Committer: andrewammerlaan X-VCS-Committer-Name: Andrew Ammerlaan X-VCS-Revision: cec003e759481c0070e3e366b33bb8504aeb046d X-VCS-Branch: master Date: Tue, 12 May 2020 09:01:53 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Archives-Salt: d75b768e-6b92-415b-9884-f13e66a52680 X-Archives-Hash: cdb47c0eb4c7d911567ebfde833c60a5 commit: cec003e759481c0070e3e366b33bb8504aeb046d Author: Huang Rui gmail com> AuthorDate: Tue May 12 03:56:26 2020 +0000 Commit: Andrew Ammerlaan riseup net> CommitDate: Tue May 12 03:56:26 2020 +0000 URL: https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=cec003e7 sci-electronics/verilator: bump to version 4.034 Verilator: Verilator 4.034 Released Package-Manager: Portage-2.3.99, Repoman-2.3.22 Signed-off-by: Huang Rui gmail.com> sci-electronics/verilator/Manifest | 1 + sci-electronics/verilator/verilator-4.034.ebuild | 39 ++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/sci-electronics/verilator/Manifest b/sci-electronics/verilator/Manifest index 82e2bf7..6161f9b 100644 --- a/sci-electronics/verilator/Manifest +++ b/sci-electronics/verilator/Manifest @@ -1 +1,2 @@ DIST verilator-4.032.tar.gz 2497830 BLAKE2B eb318e0326be9f72b32bd98f8a6de74516bda4bdf2d21d572c72e92759a4ee64e514fdb3dae20c8bea40e72d493775a02766e7ea619dd8eb541f3450278b0b20 SHA512 2b34d0b6d94babb74b443b3f3ae4e6c9f15423a0b078df72930c4f75b4a831843a4d4b901dc586725a67a49c6f5308402fef4c9ca72b88b13b01746b36d2fb20 +DIST verilator-4.034.tar.gz 2612571 BLAKE2B ff4fd49f3ef09fb17c7cce799b2c39f89ce327245b11d2f6ab9a6644e04654d637be4689e4b8d8841e37c889f7d614a41b9e475a276de8adf80587cf14fc9d3b SHA512 04c9c0f51c5c8262cd8e8338204ed6729a3f5be399e012252dd2c102f6474a9abcfdb693bc13eb4fcf7e74e0a6dfa375c3b6592fbc5b5ad2ed07f852a4a06646 diff --git a/sci-electronics/verilator/verilator-4.034.ebuild b/sci-electronics/verilator/verilator-4.034.ebuild new file mode 100644 index 0000000..10df066 --- /dev/null +++ b/sci-electronics/verilator/verilator-4.034.ebuild @@ -0,0 +1,39 @@ +# Copyright 1999-2020 Gentoo Authors +# Distributed under the terms of the GNU General Public License v2 + +EAPI="7" + +inherit autotools + +DESCRIPTION="The fast free Verilog/SystemVerilog simulator" +HOMEPAGE="https://www.veripool.org/wiki/verilator" + +if [[ "${PV}" == "9999" ]] ; then + inherit git-r3 + EGIT_REPO_URI="https://git.veripool.org/git/${PN}" +else + SRC_URI="http://www.veripool.org/ftp/${P}.tgz -> ${P}.tar.gz" + KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86" +fi + +LICENSE="|| ( Artistic-2 LGPL-3 )" +SLOT="0" + +RDEPEND=" + dev-lang/perl + sys-libs/zlib +" + +DEPEND=" + ${RDEPEND} +" + +BDEPEND=" + sys-devel/bison + sys-devel/flex +" + +src_prepare() { + default + eautoconf --force +}