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Wed, 8 Jun 2016 10:09:43 +0000 (UTC) From: "Mike Pagano" To: gentoo-commits@lists.gentoo.org Content-Transfer-Encoding: 8bit Content-type: text/plain; charset=UTF-8 Reply-To: gentoo-dev@lists.gentoo.org, "Mike Pagano" Message-ID: <1465380575.2c441aecc4fae188c2eb290024668d79d0b1a51e.mpagano@gentoo> Subject: [gentoo-commits] proj/linux-patches:4.6 commit in: / X-VCS-Repository: proj/linux-patches X-VCS-Files: 0000_README 1001_linux-4.6.2.patch X-VCS-Directories: / X-VCS-Committer: mpagano X-VCS-Committer-Name: Mike Pagano X-VCS-Revision: 2c441aecc4fae188c2eb290024668d79d0b1a51e X-VCS-Branch: 4.6 Date: Wed, 8 Jun 2016 10:09:43 +0000 (UTC) Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-commits@lists.gentoo.org X-Archives-Salt: d07d4905-f6ea-406c-aa65-94d3aadf0271 X-Archives-Hash: dff74914cbe0966ec3a5c7e418b353dc commit: 2c441aecc4fae188c2eb290024668d79d0b1a51e Author: Mike Pagano gentoo org> AuthorDate: Wed Jun 8 10:09:35 2016 +0000 Commit: Mike Pagano gentoo org> CommitDate: Wed Jun 8 10:09:35 2016 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=2c441aec Linux patch 4.6.2 0000_README | 4 + 1001_linux-4.6.2.patch | 4710 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 4714 insertions(+) diff --git a/0000_README b/0000_README index 220d627..61071b1 100644 --- a/0000_README +++ b/0000_README @@ -47,6 +47,10 @@ Patch: 1000_linux-4.6.1.patch From: http://www.kernel.org Desc: Linux 4.6.1 +Patch: 1001_linux-4.6.2.patch +From: http://www.kernel.org +Desc: Linux 4.6.2 + Patch: 1500_XATTR_USER_PREFIX.patch From: https://bugs.gentoo.org/show_bug.cgi?id=470644 Desc: Support for namespace user.pax.* on tmpfs. diff --git a/1001_linux-4.6.2.patch b/1001_linux-4.6.2.patch new file mode 100644 index 0000000..2da7598 --- /dev/null +++ b/1001_linux-4.6.2.patch @@ -0,0 +1,4710 @@ +diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl +index 1692c4dd5487..ab037f6fa2ee 100644 +--- a/Documentation/DocBook/gpu.tmpl ++++ b/Documentation/DocBook/gpu.tmpl +@@ -1623,6 +1623,12 @@ void intel_crt_init(struct drm_device *dev) + !Edrivers/gpu/drm/drm_dp_helper.c + + ++ Display Port Dual Mode Adaptor Helper Functions Reference ++!Pdrivers/gpu/drm/drm_dp_dual_mode_helper.c dp dual mode helpers ++!Iinclude/drm/drm_dp_dual_mode_helper.h ++!Edrivers/gpu/drm/drm_dp_dual_mode_helper.c ++ ++ + Display Port MST Helper Functions Reference + !Pdrivers/gpu/drm/drm_dp_mst_topology.c dp mst helper + !Iinclude/drm/drm_dp_mst_helper.h +diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt +index a70356452a82..f49783213c56 100644 +--- a/Documentation/devicetree/bindings/clock/imx35-clock.txt ++++ b/Documentation/devicetree/bindings/clock/imx35-clock.txt +@@ -94,6 +94,7 @@ clocks and IDs. + csi_sel 79 + iim_gate 80 + gpu2d_gate 81 ++ ckli_gate 82 + + Examples: + +diff --git a/Makefile b/Makefile +index 2fcc41ea99a3..93068c2d0656 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,6 +1,6 @@ + VERSION = 4 + PATCHLEVEL = 6 +-SUBLEVEL = 1 ++SUBLEVEL = 2 + EXTRAVERSION = + NAME = Charred Weasel + +@@ -364,7 +364,7 @@ AFLAGS_MODULE = + LDFLAGS_MODULE = + CFLAGS_KERNEL = + AFLAGS_KERNEL = +-CFLAGS_GCOV = -fprofile-arcs -ftest-coverage ++CFLAGS_GCOV = -fprofile-arcs -ftest-coverage -fno-tree-loop-im + CFLAGS_KCOV = -fsanitize-coverage=trace-pc + + +diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi +index 85d2c377c332..8450944b28e6 100644 +--- a/arch/arm/boot/dts/armada-385-linksys.dtsi ++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi +@@ -245,7 +245,7 @@ + button@2 { + label = "Factory Reset Button"; + linux,code = ; +- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; ++ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + +@@ -260,7 +260,7 @@ + }; + + sata { +- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +@@ -313,7 +313,7 @@ + + &pinctrl { + keys_pin: keys-pin { +- marvell,pins = "mpp24", "mpp47"; ++ marvell,pins = "mpp24", "mpp29"; + marvell,function = "gpio"; + }; + +diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +index b89e6cf1271a..7a461541ce50 100644 +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -304,13 +304,13 @@ + button@1 { + label = "WPS"; + linux,code = ; +- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; +- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; + +diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts +index 1df2f0bc1d76..a9fae910bb15 100644 +--- a/arch/arm/boot/dts/exynos4210-trats.dts ++++ b/arch/arm/boot/dts/exynos4210-trats.dts +@@ -298,6 +298,8 @@ + compatible = "maxim,max8997-pmic"; + + reg = <0x66>; ++ interrupt-parent = <&gpx0>; ++ interrupts = <7 0>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; +diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h +index b0c912feaa2f..8a394f336003 100644 +--- a/arch/arm/boot/dts/sama5d2-pinfunc.h ++++ b/arch/arm/boot/dts/sama5d2-pinfunc.h +@@ -837,8 +837,8 @@ + #define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) + #define PIN_PD24 120 + #define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +-#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD23, 1, 2) +-#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD23, 3, 3) ++#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) ++#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) + #define PIN_PD25 121 + #define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) + #define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) +diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi +index 2c8f5e6ad905..bf70d0ae93ce 100644 +--- a/arch/arm/boot/dts/sun4i-a10.dtsi ++++ b/arch/arm/boot/dts/sun4i-a10.dtsi +@@ -96,7 +96,7 @@ + allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; + clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>, <&ahb_gates 46>, +- <&dram_gates 25>, <&dram_gates 26>; ++ <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; + status = "disabled"; + }; + }; +diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi +index 0940a788f824..ee4e8e7d3e30 100644 +--- a/arch/arm/boot/dts/sun7i-a20.dtsi ++++ b/arch/arm/boot/dts/sun7i-a20.dtsi +@@ -85,8 +85,9 @@ + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; +- clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, +- <&ahb_gates 44>, <&dram_gates 26>; ++ clocks = <&pll5 1>, ++ <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, ++ <&dram_gates 5>, <&dram_gates 26>; + status = "disabled"; + }; + }; +diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c +index b955fafc58ba..d1adc59af5bf 100644 +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -31,13 +31,15 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) + } while (1); + } + ++#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) ++ + static void prom_putchar_ar71xx(unsigned char ch) + { + void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); + +- prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); ++ prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); + __raw_writel(ch, base + UART_TX * 4); +- prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); ++ prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); + } + + static void prom_putchar_ar933x(unsigned char ch) +diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h +index 867f924b05c7..e689b894353c 100644 +--- a/arch/mips/include/asm/asmmacro.h ++++ b/arch/mips/include/asm/asmmacro.h +@@ -298,21 +298,21 @@ + .set pop + .endm + +- .macro copy_u_w ws, n ++ .macro copy_s_w ws, n + .set push + .set mips32r2 + .set fp=64 + .set msa +- copy_u.w $1, $w\ws[\n] ++ copy_s.w $1, $w\ws[\n] + .set pop + .endm + +- .macro copy_u_d ws, n ++ .macro copy_s_d ws, n + .set push + .set mips64r2 + .set fp=64 + .set msa +- copy_u.d $1, $w\ws[\n] ++ copy_s.d $1, $w\ws[\n] + .set pop + .endm + +@@ -346,8 +346,8 @@ + #define STH_MSA_INSN 0x5800081f + #define STW_MSA_INSN 0x5800082f + #define STD_MSA_INSN 0x5800083f +-#define COPY_UW_MSA_INSN 0x58f00056 +-#define COPY_UD_MSA_INSN 0x58f80056 ++#define COPY_SW_MSA_INSN 0x58b00056 ++#define COPY_SD_MSA_INSN 0x58b80056 + #define INSERT_W_MSA_INSN 0x59300816 + #define INSERT_D_MSA_INSN 0x59380816 + #else +@@ -361,8 +361,8 @@ + #define STH_MSA_INSN 0x78000825 + #define STW_MSA_INSN 0x78000826 + #define STD_MSA_INSN 0x78000827 +-#define COPY_UW_MSA_INSN 0x78f00059 +-#define COPY_UD_MSA_INSN 0x78f80059 ++#define COPY_SW_MSA_INSN 0x78b00059 ++#define COPY_SD_MSA_INSN 0x78b80059 + #define INSERT_W_MSA_INSN 0x79300819 + #define INSERT_D_MSA_INSN 0x79380819 + #endif +@@ -393,7 +393,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word LDB_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -402,7 +402,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word LDH_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -411,7 +411,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word LDW_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -420,7 +420,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word LDD_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -429,7 +429,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word STB_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -438,7 +438,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word STH_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -447,7 +447,7 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word STW_MSA_INSN | (\wd << 6) + .set pop + .endm +@@ -456,26 +456,26 @@ + .set push + .set noat + SET_HARDFLOAT +- addu $1, \base, \off ++ PTR_ADDU $1, \base, \off + .word STD_MSA_INSN | (\wd << 6) + .set pop + .endm + +- .macro copy_u_w ws, n ++ .macro copy_s_w ws, n + .set push + .set noat + SET_HARDFLOAT + .insn +- .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) ++ .word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11) + .set pop + .endm + +- .macro copy_u_d ws, n ++ .macro copy_s_d ws, n + .set push + .set noat + SET_HARDFLOAT + .insn +- .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) ++ .word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11) + .set pop + .endm + +diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h +index 723229f4cf27..176de586a71a 100644 +--- a/arch/mips/include/asm/cacheflush.h ++++ b/arch/mips/include/asm/cacheflush.h +@@ -51,7 +51,6 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma, + unsigned long start, unsigned long end); + extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); + extern void __flush_dcache_page(struct page *page); +-extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page); + + #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 + static inline void flush_dcache_page(struct page *page) +@@ -77,11 +76,6 @@ static inline void flush_anon_page(struct vm_area_struct *vma, + static inline void flush_icache_page(struct vm_area_struct *vma, + struct page *page) + { +- if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) && +- Page_dcache_dirty(page)) { +- __flush_icache_page(vma, page); +- ClearPageDcacheDirty(page); +- } + } + + extern void (*flush_icache_range)(unsigned long start, unsigned long end); +diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h +index bbb85fe21642..6e4effa6f626 100644 +--- a/arch/mips/include/asm/msa.h ++++ b/arch/mips/include/asm/msa.h +@@ -147,6 +147,19 @@ static inline void restore_msa(struct task_struct *t) + _restore_msa(t); + } + ++static inline void init_msa_upper(void) ++{ ++ /* ++ * Check cpu_has_msa only if it's a constant. This will allow the ++ * compiler to optimise out code for CPUs without MSA without adding ++ * an extra redundant check for CPUs with MSA. ++ */ ++ if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa) ++ return; ++ ++ _init_msa_upper(); ++} ++ + #ifdef TOOLCHAIN_SUPPORTS_MSA + + #define __BUILD_MSA_CTL_REG(name, cs) \ +diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h +index 9a4fe0133ff1..65bf2c065db5 100644 +--- a/arch/mips/include/asm/pgtable.h ++++ b/arch/mips/include/asm/pgtable.h +@@ -127,10 +127,14 @@ do { \ + } \ + } while(0) + ++static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, ++ pte_t *ptep, pte_t pteval); ++ + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) + + #define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL)) + #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) ++#define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC) + + static inline void set_pte(pte_t *ptep, pte_t pte) + { +@@ -148,7 +152,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte) + buddy->pte_high |= _PAGE_GLOBAL; + } + } +-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) + + static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) + { +@@ -166,6 +169,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt + + #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) + #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) ++#define pte_no_exec(pte) (pte_val(pte) & _PAGE_NO_EXEC) + + /* + * Certain architectures need to do special things when pte's +@@ -218,7 +222,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) + } + #endif + } +-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) + + static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) + { +@@ -234,6 +237,22 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt + } + #endif + ++static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, ++ pte_t *ptep, pte_t pteval) ++{ ++ extern void __update_cache(unsigned long address, pte_t pte); ++ ++ if (!pte_present(pteval)) ++ goto cache_sync_done; ++ ++ if (pte_present(*ptep) && (pte_pfn(*ptep) == pte_pfn(pteval))) ++ goto cache_sync_done; ++ ++ __update_cache(addr, pteval); ++cache_sync_done: ++ set_pte(ptep, pteval); ++} ++ + /* + * (pmds are folded into puds so this doesn't get actually called, + * but the define is needed for a generic inline function.) +@@ -430,15 +449,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) + + extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, + pte_t pte); +-extern void __update_cache(struct vm_area_struct *vma, unsigned long address, +- pte_t pte); + + static inline void update_mmu_cache(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep) + { + pte_t pte = *ptep; + __update_tlb(vma, address, pte); +- __update_cache(vma, address, pte); + } + + static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, +diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h +index 28b5d84a5022..ebb5c0f2f90d 100644 +--- a/arch/mips/include/asm/switch_to.h ++++ b/arch/mips/include/asm/switch_to.h +@@ -105,7 +105,7 @@ do { \ + __clear_software_ll_bit(); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(task_thread_info(next)->tp_value); \ +- __restore_watch(); \ ++ __restore_watch(next); \ + (last) = resume(prev, next, task_thread_info(next)); \ + } while (0) + +diff --git a/arch/mips/include/asm/watch.h b/arch/mips/include/asm/watch.h +index 20126ec79359..6ffe3eadf105 100644 +--- a/arch/mips/include/asm/watch.h ++++ b/arch/mips/include/asm/watch.h +@@ -12,21 +12,21 @@ + + #include + +-void mips_install_watch_registers(void); ++void mips_install_watch_registers(struct task_struct *t); + void mips_read_watch_registers(void); + void mips_clear_watch_registers(void); + void mips_probe_watch_registers(struct cpuinfo_mips *c); + + #ifdef CONFIG_HARDWARE_WATCHPOINTS +-#define __restore_watch() do { \ ++#define __restore_watch(task) do { \ + if (unlikely(test_bit(TIF_LOAD_WATCH, \ +- ¤t_thread_info()->flags))) { \ +- mips_install_watch_registers(); \ ++ &task_thread_info(task)->flags))) { \ ++ mips_install_watch_registers(task); \ + } \ + } while (0) + + #else +-#define __restore_watch() do {} while (0) ++#define __restore_watch(task) do {} while (0) + #endif + + #endif /* _ASM_WATCH_H */ +diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h +index cc49dc240d67..8069cf766603 100644 +--- a/arch/mips/include/uapi/asm/siginfo.h ++++ b/arch/mips/include/uapi/asm/siginfo.h +@@ -28,7 +28,7 @@ + + #define __ARCH_SIGSYS + +-#include ++#include + + /* We can't use generic siginfo_t, because our si_code and si_errno are swapped */ + typedef struct siginfo { +@@ -42,13 +42,13 @@ typedef struct siginfo { + + /* kill() */ + struct { +- pid_t _pid; /* sender's pid */ ++ __kernel_pid_t _pid; /* sender's pid */ + __ARCH_SI_UID_T _uid; /* sender's uid */ + } _kill; + + /* POSIX.1b timers */ + struct { +- timer_t _tid; /* timer id */ ++ __kernel_timer_t _tid; /* timer id */ + int _overrun; /* overrun count */ + char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; + sigval_t _sigval; /* same as below */ +@@ -57,26 +57,26 @@ typedef struct siginfo { + + /* POSIX.1b signals */ + struct { +- pid_t _pid; /* sender's pid */ ++ __kernel_pid_t _pid; /* sender's pid */ + __ARCH_SI_UID_T _uid; /* sender's uid */ + sigval_t _sigval; + } _rt; + + /* SIGCHLD */ + struct { +- pid_t _pid; /* which child */ ++ __kernel_pid_t _pid; /* which child */ + __ARCH_SI_UID_T _uid; /* sender's uid */ + int _status; /* exit code */ +- clock_t _utime; +- clock_t _stime; ++ __kernel_clock_t _utime; ++ __kernel_clock_t _stime; + } _sigchld; + + /* IRIX SIGCHLD */ + struct { +- pid_t _pid; /* which child */ +- clock_t _utime; ++ __kernel_pid_t _pid; /* which child */ ++ __kernel_clock_t _utime; + int _status; /* exit code */ +- clock_t _stime; ++ __kernel_clock_t _stime; + } _irix_sigchld; + + /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ +@@ -123,6 +123,4 @@ typedef struct siginfo { + #define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */ + #define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */ + +-#include +- + #endif /* _UAPI_ASM_SIGINFO_H */ +diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c +index 3fff89ae760b..625ee770b1aa 100644 +--- a/arch/mips/kernel/mips-r2-to-r6-emul.c ++++ b/arch/mips/kernel/mips-r2-to-r6-emul.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -1251,10 +1252,10 @@ fpu_emul: + " j 10b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1326,10 +1327,10 @@ fpu_emul: + " j 10b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1397,10 +1398,10 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1467,10 +1468,10 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1582,14 +1583,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1701,14 +1702,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1820,14 +1821,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -1938,14 +1939,14 @@ fpu_emul: + " j 9b\n" + " .previous\n" + " .section __ex_table,\"a\"\n" +- " .word 1b,8b\n" +- " .word 2b,8b\n" +- " .word 3b,8b\n" +- " .word 4b,8b\n" +- " .word 5b,8b\n" +- " .word 6b,8b\n" +- " .word 7b,8b\n" +- " .word 0b,8b\n" ++ STR(PTR) " 1b,8b\n" ++ STR(PTR) " 2b,8b\n" ++ STR(PTR) " 3b,8b\n" ++ STR(PTR) " 4b,8b\n" ++ STR(PTR) " 5b,8b\n" ++ STR(PTR) " 6b,8b\n" ++ STR(PTR) " 7b,8b\n" ++ STR(PTR) " 0b,8b\n" + " .previous\n" + " .set pop\n" + : "+&r"(rt), "=&r"(rs), +@@ -2000,7 +2001,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "=&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV) +@@ -2058,7 +2059,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "+&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV)); +@@ -2119,7 +2120,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "=&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV) +@@ -2182,7 +2183,7 @@ fpu_emul: + "j 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" +- ".word 1b, 3b\n" ++ STR(PTR) " 1b,3b\n" + ".previous\n" + : "+&r"(res), "+&r"(err) + : "r"(vaddr), "i"(SIGSEGV)); +diff --git a/arch/mips/kernel/pm.c b/arch/mips/kernel/pm.c +index fefdf39d3df3..dc814892133c 100644 +--- a/arch/mips/kernel/pm.c ++++ b/arch/mips/kernel/pm.c +@@ -56,7 +56,7 @@ static void mips_cpu_restore(void) + write_c0_userlocal(current_thread_info()->tp_value); + + /* Restore watch registers */ +- __restore_watch(); ++ __restore_watch(current); + } + + /** +diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c +index 92880cee449e..d83730cd2719 100644 +--- a/arch/mips/kernel/process.c ++++ b/arch/mips/kernel/process.c +@@ -455,7 +455,7 @@ unsigned long notrace unwind_stack_by_address(unsigned long stack_page, + *sp + sizeof(*regs) <= stack_page + THREAD_SIZE - 32) { + regs = (struct pt_regs *)*sp; + pc = regs->cp0_epc; +- if (__kernel_text_address(pc)) { ++ if (!user_mode(regs) && __kernel_text_address(pc)) { + *sp = regs->regs[29]; + *ra = regs->regs[31]; + return pc; +@@ -580,11 +580,19 @@ int mips_get_process_fp_mode(struct task_struct *task) + return value; + } + ++static void prepare_for_fp_mode_switch(void *info) ++{ ++ struct mm_struct *mm = info; ++ ++ if (current->mm == mm) ++ lose_fpu(1); ++} ++ + int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) + { + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; +- unsigned long switch_count; + struct task_struct *t; ++ int max_users; + + /* Check the value is valid */ + if (value & ~known_bits) +@@ -601,6 +609,9 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) + if (!(value & PR_FP_MODE_FR) && cpu_has_fpu && cpu_has_mips_r6) + return -EOPNOTSUPP; + ++ /* Proceed with the mode switch */ ++ preempt_disable(); ++ + /* Save FP & vector context, then disable FPU & MSA */ + if (task->signal == current->signal) + lose_fpu(1); +@@ -610,31 +621,17 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) + smp_mb__after_atomic(); + + /* +- * If there are multiple online CPUs then wait until all threads whose +- * FP mode is about to change have been context switched. This approach +- * allows us to only worry about whether an FP mode switch is in +- * progress when FP is first used in a tasks time slice. Pretty much all +- * of the mode switch overhead can thus be confined to cases where mode +- * switches are actually occurring. That is, to here. However for the +- * thread performing the mode switch it may take a while... ++ * If there are multiple online CPUs then force any which are running ++ * threads in this process to lose their FPU context, which they can't ++ * regain until fp_mode_switching is cleared later. + */ + if (num_online_cpus() > 1) { +- spin_lock_irq(&task->sighand->siglock); +- +- for_each_thread(task, t) { +- if (t == current) +- continue; +- +- switch_count = t->nvcsw + t->nivcsw; ++ /* No need to send an IPI for the local CPU */ ++ max_users = (task->mm == current->mm) ? 1 : 0; + +- do { +- spin_unlock_irq(&task->sighand->siglock); +- cond_resched(); +- spin_lock_irq(&task->sighand->siglock); +- } while ((t->nvcsw + t->nivcsw) == switch_count); +- } +- +- spin_unlock_irq(&task->sighand->siglock); ++ if (atomic_read(¤t->mm->mm_users) > max_users) ++ smp_call_function(prepare_for_fp_mode_switch, ++ (void *)current->mm, 1); + } + + /* +@@ -659,6 +656,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) + + /* Allow threads to use FP again */ + atomic_set(&task->mm->context.fp_mode_switching, 0); ++ preempt_enable(); + + return 0; + } +diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c +index a5279b2f3198..4285d8b7c566 100644 +--- a/arch/mips/kernel/ptrace.c ++++ b/arch/mips/kernel/ptrace.c +@@ -57,8 +57,7 @@ static void init_fp_ctx(struct task_struct *target) + /* Begin with data registers set to all 1s... */ + memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); + +- /* ...and FCSR zeroed */ +- target->thread.fpu.fcr31 = 0; ++ /* FCSR has been preset by `mips_set_personality_nan'. */ + + /* + * Record that the target has "used" math, such that the context +@@ -80,6 +79,22 @@ void ptrace_disable(struct task_struct *child) + } + + /* ++ * Poke at FCSR according to its mask. Don't set the cause bits as ++ * this is currently not handled correctly in FP context restoration ++ * and will cause an oops if a corresponding enable bit is set. ++ */ ++static void ptrace_setfcr31(struct task_struct *child, u32 value) ++{ ++ u32 fcr31; ++ u32 mask; ++ ++ value &= ~FPU_CSR_ALL_X; ++ fcr31 = child->thread.fpu.fcr31; ++ mask = boot_cpu_data.fpu_msk31; ++ child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); ++} ++ ++/* + * Read a general register set. We always use the 64-bit format, even + * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. + * Registers are sign extended to fill the available space. +@@ -159,9 +174,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) + { + union fpureg *fregs; + u64 fpr_val; +- u32 fcr31; + u32 value; +- u32 mask; + int i; + + if (!access_ok(VERIFY_READ, data, 33 * 8)) +@@ -176,9 +189,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) + } + + __get_user(value, data + 64); +- fcr31 = child->thread.fpu.fcr31; +- mask = boot_cpu_data.fpu_msk31; +- child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); ++ ptrace_setfcr31(child, value); + + /* FIR may not be written. */ + +@@ -805,7 +816,7 @@ long arch_ptrace(struct task_struct *child, long request, + break; + #endif + case FPC_CSR: +- child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X; ++ ptrace_setfcr31(child, data); + break; + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; +diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S +index 17732f876eff..56d86b09c917 100644 +--- a/arch/mips/kernel/r4k_fpu.S ++++ b/arch/mips/kernel/r4k_fpu.S +@@ -244,17 +244,17 @@ LEAF(\name) + .set push + .set noat + #ifdef CONFIG_64BIT +- copy_u_d \wr, 1 ++ copy_s_d \wr, 1 + EX sd $1, \off(\base) + #elif defined(CONFIG_CPU_LITTLE_ENDIAN) +- copy_u_w \wr, 2 ++ copy_s_w \wr, 2 + EX sw $1, \off(\base) +- copy_u_w \wr, 3 ++ copy_s_w \wr, 3 + EX sw $1, (\off+4)(\base) + #else /* CONFIG_CPU_BIG_ENDIAN */ +- copy_u_w \wr, 2 ++ copy_s_w \wr, 2 + EX sw $1, (\off+4)(\base) +- copy_u_w \wr, 3 ++ copy_s_w \wr, 3 + EX sw $1, \off(\base) + #endif + .set pop +diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c +index 4f607341a793..d20caacfdbd3 100644 +--- a/arch/mips/kernel/setup.c ++++ b/arch/mips/kernel/setup.c +@@ -706,6 +706,9 @@ static void __init arch_mem_init(char **cmdline_p) + for_each_memblock(reserved, reg) + if (reg->size != 0) + reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT); ++ ++ reserve_bootmem_region(__pa_symbol(&__nosave_begin), ++ __pa_symbol(&__nosave_end)); /* Reserve for hibernation */ + } + + static void __init resource_init(void) +diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c +index bf792e2839a6..9e35b6b26aa8 100644 +--- a/arch/mips/kernel/signal.c ++++ b/arch/mips/kernel/signal.c +@@ -195,6 +195,9 @@ static int restore_msa_extcontext(void __user *buf, unsigned int size) + unsigned int csr; + int i, err; + ++ if (!config_enabled(CONFIG_CPU_HAS_MSA)) ++ return SIGSYS; ++ + if (size != sizeof(*msa)) + return -EINVAL; + +@@ -398,8 +401,8 @@ int protected_restore_fp_context(void __user *sc) + } + + fp_done: +- if (used & USED_EXTCONTEXT) +- err |= restore_extcontext(sc_to_extcontext(sc)); ++ if (!err && (used & USED_EXTCONTEXT)) ++ err = restore_extcontext(sc_to_extcontext(sc)); + + return err ?: sig; + } +@@ -767,15 +770,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) + sigset_t *oldset = sigmask_to_save(); + int ret; + struct mips_abi *abi = current->thread.abi; +-#ifdef CONFIG_CPU_MICROMIPS +- void *vdso; +- unsigned long tmp = (unsigned long)current->mm->context.vdso; +- +- set_isa16_mode(tmp); +- vdso = (void *)tmp; +-#else + void *vdso = current->mm->context.vdso; +-#endif + + if (regs->regs[0]) { + switch(regs->regs[2]) { +diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c +index ae0c89d23ad7..5aa1d5c2659a 100644 +--- a/arch/mips/kernel/traps.c ++++ b/arch/mips/kernel/traps.c +@@ -145,7 +145,7 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) + if (!task) + task = current; + +- if (raw_show_trace || !__kernel_text_address(pc)) { ++ if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { + show_raw_backtrace(sp); + return; + } +@@ -1249,7 +1249,7 @@ static int enable_restore_fp_context(int msa) + err = init_fpu(); + if (msa && !err) { + enable_msa(); +- _init_msa_upper(); ++ init_msa_upper(); + set_thread_flag(TIF_USEDMSA); + set_thread_flag(TIF_MSA_CTX_LIVE); + } +@@ -1312,7 +1312,7 @@ static int enable_restore_fp_context(int msa) + */ + prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); + if (!prior_msa && was_fpu_owner) { +- _init_msa_upper(); ++ init_msa_upper(); + + goto out; + } +@@ -1329,7 +1329,7 @@ static int enable_restore_fp_context(int msa) + * of each vector register such that it cannot see data left + * behind by another task. + */ +- _init_msa_upper(); ++ init_msa_upper(); + } else { + /* We need to restore the vector context. */ + restore_msa(current); +diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c +index 2a03abb5bd2c..9b78e375118e 100644 +--- a/arch/mips/kernel/watch.c ++++ b/arch/mips/kernel/watch.c +@@ -15,10 +15,9 @@ + * Install the watch registers for the current thread. A maximum of + * four registers are installed although the machine may have more. + */ +-void mips_install_watch_registers(void) ++void mips_install_watch_registers(struct task_struct *t) + { +- struct mips3264_watch_reg_state *watches = +- ¤t->thread.watch.mips3264; ++ struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264; + switch (current_cpu_data.watch_reg_use_cnt) { + default: + BUG(); +diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c +index beb80f316095..927dc94a030f 100644 +--- a/arch/mips/lib/ashldi3.c ++++ b/arch/mips/lib/ashldi3.c +@@ -2,7 +2,7 @@ + + #include "libgcc.h" + +-long long __ashldi3(long long u, word_type b) ++long long notrace __ashldi3(long long u, word_type b) + { + DWunion uu, w; + word_type bm; +diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c +index c884a912b660..9fdf1a598428 100644 +--- a/arch/mips/lib/ashrdi3.c ++++ b/arch/mips/lib/ashrdi3.c +@@ -2,7 +2,7 @@ + + #include "libgcc.h" + +-long long __ashrdi3(long long u, word_type b) ++long long notrace __ashrdi3(long long u, word_type b) + { + DWunion uu, w; + word_type bm; +diff --git a/arch/mips/lib/bswapdi.c b/arch/mips/lib/bswapdi.c +index 77e5f9c1f005..e3e77aa52c95 100644 +--- a/arch/mips/lib/bswapdi.c ++++ b/arch/mips/lib/bswapdi.c +@@ -1,6 +1,6 @@ + #include + +-unsigned long long __bswapdi2(unsigned long long u) ++unsigned long long notrace __bswapdi2(unsigned long long u) + { + return (((u) & 0xff00000000000000ull) >> 56) | + (((u) & 0x00ff000000000000ull) >> 40) | +diff --git a/arch/mips/lib/bswapsi.c b/arch/mips/lib/bswapsi.c +index 2b302ff121d2..530a8afe6fda 100644 +--- a/arch/mips/lib/bswapsi.c ++++ b/arch/mips/lib/bswapsi.c +@@ -1,6 +1,6 @@ + #include + +-unsigned int __bswapsi2(unsigned int u) ++unsigned int notrace __bswapsi2(unsigned int u) + { + return (((u) & 0xff000000) >> 24) | + (((u) & 0x00ff0000) >> 8) | +diff --git a/arch/mips/lib/cmpdi2.c b/arch/mips/lib/cmpdi2.c +index 8c1306437ed1..06857da96993 100644 +--- a/arch/mips/lib/cmpdi2.c ++++ b/arch/mips/lib/cmpdi2.c +@@ -2,7 +2,7 @@ + + #include "libgcc.h" + +-word_type __cmpdi2(long long a, long long b) ++word_type notrace __cmpdi2(long long a, long long b) + { + const DWunion au = { + .ll = a +diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c +index dcf8d6810b7c..364547449c65 100644 +--- a/arch/mips/lib/lshrdi3.c ++++ b/arch/mips/lib/lshrdi3.c +@@ -2,7 +2,7 @@ + + #include "libgcc.h" + +-long long __lshrdi3(long long u, word_type b) ++long long notrace __lshrdi3(long long u, word_type b) + { + DWunion uu, w; + word_type bm; +diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c +index bb4cb2f828ea..bd599f58234c 100644 +--- a/arch/mips/lib/ucmpdi2.c ++++ b/arch/mips/lib/ucmpdi2.c +@@ -2,7 +2,7 @@ + + #include "libgcc.h" + +-word_type __ucmpdi2(unsigned long long a, unsigned long long b) ++word_type notrace __ucmpdi2(unsigned long long a, unsigned long long b) + { + const DWunion au = {.ll = a}; + const DWunion bu = {.ll = b}; +diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform +index 85d808924c94..0fce4608aa88 100644 +--- a/arch/mips/loongson64/Platform ++++ b/arch/mips/loongson64/Platform +@@ -31,7 +31,7 @@ cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap + # can't easily be used safely within the kbuild framework. + # + ifeq ($(call cc-ifversion, -ge, 0409, y), y) +- ifeq ($(call ld-ifversion, -ge, 22500000, y), y) ++ ifeq ($(call ld-ifversion, -ge, 225000000, y), y) + cflags-$(CONFIG_CPU_LOONGSON3) += \ + $(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) + else +diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/loongson-3/numa.c +index 6f9e010cec4d..282c5a8c2fcd 100644 +--- a/arch/mips/loongson64/loongson-3/numa.c ++++ b/arch/mips/loongson64/loongson-3/numa.c +@@ -213,10 +213,10 @@ static void __init node_mem_init(unsigned int node) + BOOTMEM_DEFAULT); + + if (node == 0 && node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT)) { +- /* Reserve 0xff800000~0xffffffff for RS780E integrated GPU */ ++ /* Reserve 0xfe000000~0xffffffff for RS780E integrated GPU */ + reserve_bootmem_node(NODE_DATA(node), +- (node_addrspace_offset | 0xff800000), +- 8 << 20, BOOTMEM_DEFAULT); ++ (node_addrspace_offset | 0xfe000000), ++ 32 << 20, BOOTMEM_DEFAULT); + } + + sparse_memory_present_with_active_regions(node); +diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c +index cdfd44ffa51c..41d3e0e7defa 100644 +--- a/arch/mips/math-emu/cp1emu.c ++++ b/arch/mips/math-emu/cp1emu.c +@@ -445,9 +445,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + case spec_op: + switch (insn.r_format.func) { + case jalr_op: +- regs->regs[insn.r_format.rd] = +- regs->cp0_epc + dec_insn.pc_inc + +- dec_insn.next_pc_inc; ++ if (insn.r_format.rd != 0) { ++ regs->regs[insn.r_format.rd] = ++ regs->cp0_epc + dec_insn.pc_inc + ++ dec_insn.next_pc_inc; ++ } + /* Fall through */ + case jr_op: + /* For R6, JR already emulated in jalr_op */ +diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c +index 3f159caf6dbc..bf04c6c479a4 100644 +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -16,6 +16,7 @@ + #include + + #include ++#include + #include + #include + #include +@@ -83,8 +84,6 @@ void __flush_dcache_page(struct page *page) + struct address_space *mapping = page_mapping(page); + unsigned long addr; + +- if (PageHighMem(page)) +- return; + if (mapping && !mapping_mapped(mapping)) { + SetPageDcacheDirty(page); + return; +@@ -95,8 +94,15 @@ void __flush_dcache_page(struct page *page) + * case is for exec env/arg pages and those are %99 certainly going to + * get faulted into the tlb (and thus flushed) anyways. + */ +- addr = (unsigned long) page_address(page); ++ if (PageHighMem(page)) ++ addr = (unsigned long)kmap_atomic(page); ++ else ++ addr = (unsigned long)page_address(page); ++ + flush_data_cache_page(addr); ++ ++ if (PageHighMem(page)) ++ __kunmap_atomic((void *)addr); + } + + EXPORT_SYMBOL(__flush_dcache_page); +@@ -119,33 +125,28 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr) + + EXPORT_SYMBOL(__flush_anon_page); + +-void __flush_icache_page(struct vm_area_struct *vma, struct page *page) +-{ +- unsigned long addr; +- +- if (PageHighMem(page)) +- return; +- +- addr = (unsigned long) page_address(page); +- flush_data_cache_page(addr); +-} +-EXPORT_SYMBOL_GPL(__flush_icache_page); +- +-void __update_cache(struct vm_area_struct *vma, unsigned long address, +- pte_t pte) ++void __update_cache(unsigned long address, pte_t pte) + { + struct page *page; + unsigned long pfn, addr; +- int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc; ++ int exec = !pte_no_exec(pte) && !cpu_has_ic_fills_f_dc; + + pfn = pte_pfn(pte); + if (unlikely(!pfn_valid(pfn))) + return; + page = pfn_to_page(pfn); +- if (page_mapping(page) && Page_dcache_dirty(page)) { +- addr = (unsigned long) page_address(page); ++ if (Page_dcache_dirty(page)) { ++ if (PageHighMem(page)) ++ addr = (unsigned long)kmap_atomic(page); ++ else ++ addr = (unsigned long)page_address(page); ++ + if (exec || pages_do_alias(addr, address & PAGE_MASK)) + flush_data_cache_page(addr); ++ ++ if (PageHighMem(page)) ++ __kunmap_atomic((void *)addr); ++ + ClearPageDcacheDirty(page); + } + } +diff --git a/arch/mips/vdso/Makefile b/arch/mips/vdso/Makefile +index ee3617c0c5e2..f37e6ba40f52 100644 +--- a/arch/mips/vdso/Makefile ++++ b/arch/mips/vdso/Makefile +@@ -5,10 +5,12 @@ obj-vdso-y := elf.o gettimeofday.o sigreturn.o + ccflags-vdso := \ + $(filter -I%,$(KBUILD_CFLAGS)) \ + $(filter -E%,$(KBUILD_CFLAGS)) \ ++ $(filter -mmicromips,$(KBUILD_CFLAGS)) \ + $(filter -march=%,$(KBUILD_CFLAGS)) + cflags-vdso := $(ccflags-vdso) \ + $(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \ +- -O2 -g -fPIC -fno-common -fno-builtin -G 0 -DDISABLE_BRANCH_PROFILING \ ++ -O2 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \ ++ -DDISABLE_BRANCH_PROFILING \ + $(call cc-option, -fno-stack-protector) + aflags-vdso := $(ccflags-vdso) \ + $(filter -I%,$(KBUILD_CFLAGS)) \ +diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c +index 6544017eb90b..67584847973a 100644 +--- a/arch/powerpc/kernel/eeh.c ++++ b/arch/powerpc/kernel/eeh.c +@@ -1068,7 +1068,7 @@ void eeh_add_device_early(struct pci_dn *pdn) + struct pci_controller *phb; + struct eeh_dev *edev = pdn_to_eeh_dev(pdn); + +- if (!edev || !eeh_enabled()) ++ if (!edev) + return; + + if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) +diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c +index fb6207d2c604..31e4c7e1a4b4 100644 +--- a/arch/powerpc/kernel/eeh_driver.c ++++ b/arch/powerpc/kernel/eeh_driver.c +@@ -171,6 +171,16 @@ static void *eeh_dev_save_state(void *data, void *userdata) + if (!edev) + return NULL; + ++ /* ++ * We cannot access the config space on some adapters. ++ * Otherwise, it will cause fenced PHB. We don't save ++ * the content in their config space and will restore ++ * from the initial config space saved when the EEH ++ * device is created. ++ */ ++ if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED)) ++ return NULL; ++ + pdev = eeh_dev_to_pci_dev(edev); + if (!pdev) + return NULL; +@@ -312,6 +322,19 @@ static void *eeh_dev_restore_state(void *data, void *userdata) + if (!edev) + return NULL; + ++ /* ++ * The content in the config space isn't saved because ++ * the blocked config space on some adapters. We have ++ * to restore the initial saved config space when the ++ * EEH device is created. ++ */ ++ if (edev->pe && (edev->pe->state & EEH_PE_CFG_RESTRICTED)) { ++ if (list_is_last(&edev->list, &edev->pe->edevs)) ++ eeh_pe_restore_bars(edev->pe); ++ ++ return NULL; ++ } ++ + pdev = eeh_dev_to_pci_dev(edev); + if (!pdev) + return NULL; +@@ -564,9 +587,6 @@ int eeh_pe_reset_and_recover(struct eeh_pe *pe) + /* Save states */ + eeh_pe_dev_traverse(pe, eeh_dev_save_state, NULL); + +- /* Report error */ +- eeh_pe_dev_traverse(pe, eeh_report_error, &result); +- + /* Issue reset */ + ret = eeh_reset_pe(pe); + if (ret) { +diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S +index 7716cebf4b8e..2b66f25d40db 100644 +--- a/arch/powerpc/kernel/exceptions-64s.S ++++ b/arch/powerpc/kernel/exceptions-64s.S +@@ -953,11 +953,6 @@ hv_facility_unavailable_relon_trampoline: + #endif + STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist) + +- /* Other future vectors */ +- .align 7 +- .globl __end_interrupts +-__end_interrupts: +- + .align 7 + system_call_entry: + b system_call_common +@@ -1244,6 +1239,17 @@ __end_handlers: + STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable) + STD_RELON_EXCEPTION_HV_OOL(0xf80, hv_facility_unavailable) + ++ /* ++ * The __end_interrupts marker must be past the out-of-line (OOL) ++ * handlers, so that they are copied to real address 0x100 when running ++ * a relocatable kernel. This ensures they can be reached from the short ++ * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch ++ * directly, without using LOAD_HANDLER(). ++ */ ++ .align 7 ++ .globl __end_interrupts ++__end_interrupts: ++ + #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) + /* + * Data area reserved for FWNMI option. +diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c +index 7ab29518a3b9..e345891450c3 100644 +--- a/arch/x86/xen/setup.c ++++ b/arch/x86/xen/setup.c +@@ -393,6 +393,9 @@ static unsigned long __init xen_set_identity_and_remap_chunk( + unsigned long i = 0; + unsigned long n = end_pfn - start_pfn; + ++ if (remap_pfn == 0) ++ remap_pfn = nr_pages; ++ + while (i < n) { + unsigned long cur_pfn = start_pfn + i; + unsigned long left = n - i; +@@ -438,17 +441,29 @@ static unsigned long __init xen_set_identity_and_remap_chunk( + return remap_pfn; + } + +-static void __init xen_set_identity_and_remap(unsigned long nr_pages) ++static unsigned long __init xen_count_remap_pages( ++ unsigned long start_pfn, unsigned long end_pfn, unsigned long nr_pages, ++ unsigned long remap_pages) ++{ ++ if (start_pfn >= nr_pages) ++ return remap_pages; ++ ++ return remap_pages + min(end_pfn, nr_pages) - start_pfn; ++} ++ ++static unsigned long __init xen_foreach_remap_area(unsigned long nr_pages, ++ unsigned long (*func)(unsigned long start_pfn, unsigned long end_pfn, ++ unsigned long nr_pages, unsigned long last_val)) + { + phys_addr_t start = 0; +- unsigned long last_pfn = nr_pages; ++ unsigned long ret_val = 0; + const struct e820entry *entry = xen_e820_map; + int i; + + /* + * Combine non-RAM regions and gaps until a RAM region (or the +- * end of the map) is reached, then set the 1:1 map and +- * remap the memory in those non-RAM regions. ++ * end of the map) is reached, then call the provided function ++ * to perform its duty on the non-RAM region. + * + * The combined non-RAM regions are rounded to a whole number + * of pages so any partial pages are accessible via the 1:1 +@@ -466,14 +481,13 @@ static void __init xen_set_identity_and_remap(unsigned long nr_pages) + end_pfn = PFN_UP(entry->addr); + + if (start_pfn < end_pfn) +- last_pfn = xen_set_identity_and_remap_chunk( +- start_pfn, end_pfn, nr_pages, +- last_pfn); ++ ret_val = func(start_pfn, end_pfn, nr_pages, ++ ret_val); + start = end; + } + } + +- pr_info("Released %ld page(s)\n", xen_released_pages); ++ return ret_val; + } + + /* +@@ -596,35 +610,6 @@ static void __init xen_ignore_unusable(void) + } + } + +-static unsigned long __init xen_count_remap_pages(unsigned long max_pfn) +-{ +- unsigned long extra = 0; +- unsigned long start_pfn, end_pfn; +- const struct e820entry *entry = xen_e820_map; +- int i; +- +- end_pfn = 0; +- for (i = 0; i < xen_e820_map_entries; i++, entry++) { +- start_pfn = PFN_DOWN(entry->addr); +- /* Adjacent regions on non-page boundaries handling! */ +- end_pfn = min(end_pfn, start_pfn); +- +- if (start_pfn >= max_pfn) +- return extra + max_pfn - end_pfn; +- +- /* Add any holes in map to result. */ +- extra += start_pfn - end_pfn; +- +- end_pfn = PFN_UP(entry->addr + entry->size); +- end_pfn = min(end_pfn, max_pfn); +- +- if (entry->type != E820_RAM) +- extra += end_pfn - start_pfn; +- } +- +- return extra; +-} +- + bool __init xen_is_e820_reserved(phys_addr_t start, phys_addr_t size) + { + struct e820entry *entry; +@@ -804,7 +789,7 @@ char * __init xen_memory_setup(void) + max_pages = xen_get_max_pages(); + + /* How many extra pages do we need due to remapping? */ +- max_pages += xen_count_remap_pages(max_pfn); ++ max_pages += xen_foreach_remap_area(max_pfn, xen_count_remap_pages); + + if (max_pages > max_pfn) + extra_pages += max_pages - max_pfn; +@@ -922,7 +907,9 @@ char * __init xen_memory_setup(void) + * Set identity map on non-RAM pages and prepare remapping the + * underlying RAM. + */ +- xen_set_identity_and_remap(max_pfn); ++ xen_foreach_remap_area(max_pfn, xen_set_identity_and_remap_chunk); ++ ++ pr_info("Released %ld page(s)\n", xen_released_pages); + + return "Xen"; + } +diff --git a/crypto/asymmetric_keys/pkcs7_parser.c b/crypto/asymmetric_keys/pkcs7_parser.c +index 40de03f49ff8..bdd0d753ce5d 100644 +--- a/crypto/asymmetric_keys/pkcs7_parser.c ++++ b/crypto/asymmetric_keys/pkcs7_parser.c +@@ -237,6 +237,7 @@ int pkcs7_sig_note_digest_algo(void *context, size_t hdrlen, + break; + case OID_sha224: + ctx->sinfo->sig.hash_algo = "sha224"; ++ break; + default: + printk("Unsupported digest algo: %u\n", ctx->last_oid); + return -ENOPKG; +diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c +index 6e7c3ccea24b..27aea96036c4 100644 +--- a/drivers/base/power/main.c ++++ b/drivers/base/power/main.c +@@ -1267,14 +1267,15 @@ int dpm_suspend_late(pm_message_t state) + error = device_suspend_late(dev); + + mutex_lock(&dpm_list_mtx); ++ if (!list_empty(&dev->power.entry)) ++ list_move(&dev->power.entry, &dpm_late_early_list); ++ + if (error) { + pm_dev_err(dev, state, " late", error); + dpm_save_failed_dev(dev_name(dev)); + put_device(dev); + break; + } +- if (!list_empty(&dev->power.entry)) +- list_move(&dev->power.entry, &dpm_late_early_list); + put_device(dev); + + if (async_error) +diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c +index 4c7055009bd6..b74690418504 100644 +--- a/drivers/base/power/runtime.c ++++ b/drivers/base/power/runtime.c +@@ -1506,11 +1506,16 @@ int pm_runtime_force_resume(struct device *dev) + goto out; + } + +- ret = callback(dev); ++ ret = pm_runtime_set_active(dev); + if (ret) + goto out; + +- pm_runtime_set_active(dev); ++ ret = callback(dev); ++ if (ret) { ++ pm_runtime_set_suspended(dev); ++ goto out; ++ } ++ + pm_runtime_mark_last_busy(dev); + out: + pm_runtime_enable(dev); +diff --git a/drivers/char/hw_random/exynos-rng.c b/drivers/char/hw_random/exynos-rng.c +index ada081232528..b98a141ea89c 100644 +--- a/drivers/char/hw_random/exynos-rng.c ++++ b/drivers/char/hw_random/exynos-rng.c +@@ -89,6 +89,7 @@ static int exynos_read(struct hwrng *rng, void *buf, + struct exynos_rng, rng); + u32 *data = buf; + int retry = 100; ++ int ret = 4; + + pm_runtime_get_sync(exynos_rng->dev); + +@@ -97,17 +98,20 @@ static int exynos_read(struct hwrng *rng, void *buf, + while (!(exynos_rng_readl(exynos_rng, + EXYNOS_PRNG_STATUS_OFFSET) & PRNG_DONE) && --retry) + cpu_relax(); +- if (!retry) +- return -ETIMEDOUT; ++ if (!retry) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } + + exynos_rng_writel(exynos_rng, PRNG_DONE, EXYNOS_PRNG_STATUS_OFFSET); + + *data = exynos_rng_readl(exynos_rng, EXYNOS_PRNG_OUT1_OFFSET); + ++out: + pm_runtime_mark_last_busy(exynos_rng->dev); + pm_runtime_put_sync_autosuspend(exynos_rng->dev); + +- return 4; ++ return ret; + } + + static int exynos_rng_probe(struct platform_device *pdev) +diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c +index 819f5842fa66..8e20c8a76db7 100644 +--- a/drivers/clk/at91/clk-h32mx.c ++++ b/drivers/clk/at91/clk-h32mx.c +@@ -114,7 +114,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) + h32mxclk->regmap = regmap; + + clk = clk_register(NULL, &h32mxclk->hw); +- if (!clk) { ++ if (IS_ERR(clk)) { + kfree(h32mxclk); + return; + } +diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c +index 90338c38e38a..1f79f48d5adc 100644 +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -51,6 +51,7 @@ + #define CM_GNRICCTL 0x000 + #define CM_GNRICDIV 0x004 + # define CM_DIV_FRAC_BITS 12 ++# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) + + #define CM_VPUCTL 0x008 + #define CM_VPUDIV 0x00c +@@ -128,6 +129,7 @@ + # define CM_GATE BIT(CM_GATE_BIT) + # define CM_BUSY BIT(7) + # define CM_BUSYD BIT(8) ++# define CM_FRAC BIT(9) + # define CM_SRC_SHIFT 0 + # define CM_SRC_BITS 4 + # define CM_SRC_MASK 0xf +@@ -644,6 +646,7 @@ struct bcm2835_clock_data { + u32 frac_bits; + + bool is_vpu_clock; ++ bool is_mash_clock; + }; + + static const char *const bcm2835_clock_per_parents[] = { +@@ -825,6 +828,7 @@ static const struct bcm2835_clock_data bcm2835_clock_pwm_data = { + .div_reg = CM_PWMDIV, + .int_bits = 12, + .frac_bits = 12, ++ .is_mash_clock = true, + }; + + struct bcm2835_pll { +@@ -910,8 +914,14 @@ static void bcm2835_pll_off(struct clk_hw *hw) + struct bcm2835_cprman *cprman = pll->cprman; + const struct bcm2835_pll_data *data = pll->data; + +- cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); +- cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); ++ spin_lock(&cprman->regs_lock); ++ cprman_write(cprman, data->cm_ctrl_reg, ++ cprman_read(cprman, data->cm_ctrl_reg) | ++ CM_PLL_ANARST); ++ cprman_write(cprman, data->a2w_ctrl_reg, ++ cprman_read(cprman, data->a2w_ctrl_reg) | ++ A2W_PLL_CTRL_PWRDN); ++ spin_unlock(&cprman->regs_lock); + } + + static int bcm2835_pll_on(struct clk_hw *hw) +@@ -921,6 +931,10 @@ static int bcm2835_pll_on(struct clk_hw *hw) + const struct bcm2835_pll_data *data = pll->data; + ktime_t timeout; + ++ cprman_write(cprman, data->a2w_ctrl_reg, ++ cprman_read(cprman, data->a2w_ctrl_reg) & ++ ~A2W_PLL_CTRL_PWRDN); ++ + /* Take the PLL out of reset. */ + cprman_write(cprman, data->cm_ctrl_reg, + cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); +@@ -1174,7 +1188,7 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw, + GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; + u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; + u64 rem; +- u32 div; ++ u32 div, mindiv, maxdiv; + + rem = do_div(temp, rate); + div = temp; +@@ -1184,10 +1198,23 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw, + div += unused_frac_mask + 1; + div &= ~unused_frac_mask; + +- /* Clamp to the limits. */ +- div = max(div, unused_frac_mask + 1); +- div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, +- CM_DIV_FRAC_BITS - data->frac_bits)); ++ /* different clamping limits apply for a mash clock */ ++ if (data->is_mash_clock) { ++ /* clamp to min divider of 2 */ ++ mindiv = 2 << CM_DIV_FRAC_BITS; ++ /* clamp to the highest possible integer divider */ ++ maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; ++ } else { ++ /* clamp to min divider of 1 */ ++ mindiv = 1 << CM_DIV_FRAC_BITS; ++ /* clamp to the highest possible fractional divider */ ++ maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, ++ CM_DIV_FRAC_BITS - data->frac_bits); ++ } ++ ++ /* apply the clamping limits */ ++ div = max_t(u32, div, mindiv); ++ div = min_t(u32, div, maxdiv); + + return div; + } +@@ -1281,9 +1308,26 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, + struct bcm2835_cprman *cprman = clock->cprman; + const struct bcm2835_clock_data *data = clock->data; + u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); ++ u32 ctl; ++ ++ spin_lock(&cprman->regs_lock); ++ ++ /* ++ * Setting up frac support ++ * ++ * In principle it is recommended to stop/start the clock first, ++ * but as we set CLK_SET_RATE_GATE during registration of the ++ * clock this requirement should be take care of by the ++ * clk-framework. ++ */ ++ ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; ++ ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; ++ cprman_write(cprman, data->ctl_reg, ctl); + + cprman_write(cprman, data->div_reg, div); + ++ spin_unlock(&cprman->regs_lock); ++ + return 0; + } + +diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c +index a71d24cb4c06..b0978d3b83e2 100644 +--- a/drivers/clk/imx/clk-imx35.c ++++ b/drivers/clk/imx/clk-imx35.c +@@ -66,7 +66,7 @@ static const char *std_sel[] = {"ppll", "arm"}; + static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; + + enum mx35_clks { +- ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, ++ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, + arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, + esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, + spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, +@@ -79,7 +79,7 @@ enum mx35_clks { + rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, + ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, + wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, +- gpu2d_gate, clk_max ++ gpu2d_gate, ckil, clk_max + }; + + static struct clk *clk[clk_max]; +diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c +index f996efc56605..0db185762a10 100644 +--- a/drivers/cpuidle/cpuidle.c ++++ b/drivers/cpuidle/cpuidle.c +@@ -214,7 +214,7 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, + tick_broadcast_exit(); + } + +- if (!cpuidle_state_is_coupled(drv, entered_state)) ++ if (!cpuidle_state_is_coupled(drv, index)) + local_irq_enable(); + + diff = ktime_to_us(ktime_sub(time_end, time_start)); +@@ -433,6 +433,8 @@ static void __cpuidle_unregister_device(struct cpuidle_device *dev) + list_del(&dev->device_list); + per_cpu(cpuidle_devices, dev->cpu) = NULL; + module_put(drv->owner); ++ ++ dev->registered = 0; + } + + static void __cpuidle_device_init(struct cpuidle_device *dev) +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index 6eb94fc561dc..22228ef50f36 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -23,7 +23,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o + + drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ + drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ +- drm_kms_helper_common.o ++ drm_kms_helper_common.o drm_dp_dual_mode_helper.o + + drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o + drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +index 119cdc2c43e7..7ef2c13921b4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +@@ -194,12 +194,12 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) + bpc = 8; + DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", + connector->name, bpc); +- } else if (bpc > 8) { +- /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ +- DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", +- connector->name); +- bpc = 8; + } ++ } else if (bpc > 8) { ++ /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ ++ DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", ++ connector->name); ++ bpc = 8; + } + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +index 7b7f4aba60c0..fe36caf1b7d7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +@@ -150,7 +150,7 @@ u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { +- vrefresh = amdgpu_crtc->hw_mode.vrefresh; ++ vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); + break; + } + } +diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c +index 8ee1db866e80..d307d9627887 100644 +--- a/drivers/gpu/drm/drm_atomic.c ++++ b/drivers/gpu/drm/drm_atomic.c +@@ -139,7 +139,7 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state) + for (i = 0; i < state->num_connector; i++) { + struct drm_connector *connector = state->connectors[i]; + +- if (!connector) ++ if (!connector || !connector->funcs) + continue; + + /* +diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c b/drivers/gpu/drm/drm_dp_dual_mode_helper.c +new file mode 100644 +index 000000000000..a7b2a751f6fe +--- /dev/null ++++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c +@@ -0,0 +1,366 @@ ++/* ++ * Copyright © 2016 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/** ++ * DOC: dp dual mode helpers ++ * ++ * Helper functions to deal with DP dual mode (aka. DP++) adaptors. ++ * ++ * Type 1: ++ * Adaptor registers (if any) and the sink DDC bus may be accessed via I2C. ++ * ++ * Type 2: ++ * Adaptor registers and sink DDC bus can be accessed either via I2C or ++ * I2C-over-AUX. Source devices may choose to implement either of these ++ * access methods. ++ */ ++ ++#define DP_DUAL_MODE_SLAVE_ADDRESS 0x40 ++ ++/** ++ * drm_dp_dual_mode_read - Read from the DP dual mode adaptor register(s) ++ * @adapter: I2C adapter for the DDC bus ++ * @offset: register offset ++ * @buffer: buffer for return data ++ * @size: sizo of the buffer ++ * ++ * Reads @size bytes from the DP dual mode adaptor registers ++ * starting at @offset. ++ * ++ * Returns: ++ * 0 on success, negative error code on failure ++ */ ++ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter, ++ u8 offset, void *buffer, size_t size) ++{ ++ struct i2c_msg msgs[] = { ++ { ++ .addr = DP_DUAL_MODE_SLAVE_ADDRESS, ++ .flags = 0, ++ .len = 1, ++ .buf = &offset, ++ }, ++ { ++ .addr = DP_DUAL_MODE_SLAVE_ADDRESS, ++ .flags = I2C_M_RD, ++ .len = size, ++ .buf = buffer, ++ }, ++ }; ++ int ret; ++ ++ ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); ++ if (ret < 0) ++ return ret; ++ if (ret != ARRAY_SIZE(msgs)) ++ return -EPROTO; ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_read); ++ ++/** ++ * drm_dp_dual_mode_write - Write to the DP dual mode adaptor register(s) ++ * @adapter: I2C adapter for the DDC bus ++ * @offset: register offset ++ * @buffer: buffer for write data ++ * @size: sizo of the buffer ++ * ++ * Writes @size bytes to the DP dual mode adaptor registers ++ * starting at @offset. ++ * ++ * Returns: ++ * 0 on success, negative error code on failure ++ */ ++ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter, ++ u8 offset, const void *buffer, size_t size) ++{ ++ struct i2c_msg msg = { ++ .addr = DP_DUAL_MODE_SLAVE_ADDRESS, ++ .flags = 0, ++ .len = 1 + size, ++ .buf = NULL, ++ }; ++ void *data; ++ int ret; ++ ++ data = kmalloc(msg.len, GFP_TEMPORARY); ++ if (!data) ++ return -ENOMEM; ++ ++ msg.buf = data; ++ ++ memcpy(data, &offset, 1); ++ memcpy(data + 1, buffer, size); ++ ++ ret = i2c_transfer(adapter, &msg, 1); ++ ++ kfree(data); ++ ++ if (ret < 0) ++ return ret; ++ if (ret != 1) ++ return -EPROTO; ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_write); ++ ++static bool is_hdmi_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN]) ++{ ++ static const char dp_dual_mode_hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN] = ++ "DP-HDMI ADAPTOR\x04"; ++ ++ return memcmp(hdmi_id, dp_dual_mode_hdmi_id, ++ sizeof(dp_dual_mode_hdmi_id)) == 0; ++} ++ ++static bool is_type2_adaptor(uint8_t adaptor_id) ++{ ++ return adaptor_id == (DP_DUAL_MODE_TYPE_TYPE2 | ++ DP_DUAL_MODE_REV_TYPE2); ++} ++ ++/** ++ * drm_dp_dual_mode_detect - Identify the DP dual mode adaptor ++ * @adapter: I2C adapter for the DDC bus ++ * ++ * Attempt to identify the type of the DP dual mode adaptor used. ++ * ++ * Note that when the answer is @DRM_DP_DUAL_MODE_UNKNOWN it's not ++ * certain whether we're dealing with a native HDMI port or ++ * a type 1 DVI dual mode adaptor. The driver will have to use ++ * some other hardware/driver specific mechanism to make that ++ * distinction. ++ * ++ * Returns: ++ * The type of the DP dual mode adaptor used ++ */ ++enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(struct i2c_adapter *adapter) ++{ ++ char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN] = {}; ++ uint8_t adaptor_id = 0x00; ++ ssize_t ret; ++ ++ /* ++ * Let's see if the adaptor is there the by reading the ++ * HDMI ID registers. ++ * ++ * Note that type 1 DVI adaptors are not required to implemnt ++ * any registers, and that presents a problem for detection. ++ * If the i2c transfer is nacked, we may or may not be dealing ++ * with a type 1 DVI adaptor. Some other mechanism of detecting ++ * the presence of the adaptor is required. One way would be ++ * to check the state of the CONFIG1 pin, Another method would ++ * simply require the driver to know whether the port is a DP++ ++ * port or a native HDMI port. Both of these methods are entirely ++ * hardware/driver specific so we can't deal with them here. ++ */ ++ ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_HDMI_ID, ++ hdmi_id, sizeof(hdmi_id)); ++ if (ret) ++ return DRM_DP_DUAL_MODE_UNKNOWN; ++ ++ /* ++ * Sigh. Some (maybe all?) type 1 adaptors are broken and ack ++ * the offset but ignore it, and instead they just always return ++ * data from the start of the HDMI ID buffer. So for a broken ++ * type 1 HDMI adaptor a single byte read will always give us ++ * 0x44, and for a type 1 DVI adaptor it should give 0x00 ++ * (assuming it implements any registers). Fortunately neither ++ * of those values will match the type 2 signature of the ++ * DP_DUAL_MODE_ADAPTOR_ID register so we can proceed with ++ * the type 2 adaptor detection safely even in the presence ++ * of broken type 1 adaptors. ++ */ ++ ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_ADAPTOR_ID, ++ &adaptor_id, sizeof(adaptor_id)); ++ if (ret == 0) { ++ if (is_type2_adaptor(adaptor_id)) { ++ if (is_hdmi_adaptor(hdmi_id)) ++ return DRM_DP_DUAL_MODE_TYPE2_HDMI; ++ else ++ return DRM_DP_DUAL_MODE_TYPE2_DVI; ++ } ++ } ++ ++ if (is_hdmi_adaptor(hdmi_id)) ++ return DRM_DP_DUAL_MODE_TYPE1_HDMI; ++ else ++ return DRM_DP_DUAL_MODE_TYPE1_DVI; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_detect); ++ ++/** ++ * drm_dp_dual_mode_max_tmds_clock - Max TMDS clock for DP dual mode adaptor ++ * @type: DP dual mode adaptor type ++ * @adapter: I2C adapter for the DDC bus ++ * ++ * Determine the max TMDS clock the adaptor supports based on the ++ * type of the dual mode adaptor and the DP_DUAL_MODE_MAX_TMDS_CLOCK ++ * register (on type2 adaptors). As some type 1 adaptors have ++ * problems with registers (see comments in drm_dp_dual_mode_detect()) ++ * we don't read the register on those, instead we simply assume ++ * a 165 MHz limit based on the specification. ++ * ++ * Returns: ++ * Maximum supported TMDS clock rate for the DP dual mode adaptor in kHz. ++ */ ++int drm_dp_dual_mode_max_tmds_clock(enum drm_dp_dual_mode_type type, ++ struct i2c_adapter *adapter) ++{ ++ uint8_t max_tmds_clock; ++ ssize_t ret; ++ ++ /* native HDMI so no limit */ ++ if (type == DRM_DP_DUAL_MODE_NONE) ++ return 0; ++ ++ /* ++ * Type 1 adaptors are limited to 165MHz ++ * Type 2 adaptors can tells us their limit ++ */ ++ if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) ++ return 165000; ++ ++ ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_MAX_TMDS_CLOCK, ++ &max_tmds_clock, sizeof(max_tmds_clock)); ++ if (ret || max_tmds_clock == 0x00 || max_tmds_clock == 0xff) { ++ DRM_DEBUG_KMS("Failed to query max TMDS clock\n"); ++ return 165000; ++ } ++ ++ return max_tmds_clock * 5000 / 2; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_max_tmds_clock); ++ ++/** ++ * drm_dp_dual_mode_get_tmds_output - Get the state of the TMDS output buffers in the DP dual mode adaptor ++ * @type: DP dual mode adaptor type ++ * @adapter: I2C adapter for the DDC bus ++ * @enabled: current state of the TMDS output buffers ++ * ++ * Get the state of the TMDS output buffers in the adaptor. For ++ * type2 adaptors this is queried from the DP_DUAL_MODE_TMDS_OEN ++ * register. As some type 1 adaptors have problems with registers ++ * (see comments in drm_dp_dual_mode_detect()) we don't read the ++ * register on those, instead we simply assume that the buffers ++ * are always enabled. ++ * ++ * Returns: ++ * 0 on success, negative error code on failure ++ */ ++int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type, ++ struct i2c_adapter *adapter, ++ bool *enabled) ++{ ++ uint8_t tmds_oen; ++ ssize_t ret; ++ ++ if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) { ++ *enabled = true; ++ return 0; ++ } ++ ++ ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN, ++ &tmds_oen, sizeof(tmds_oen)); ++ if (ret) { ++ DRM_DEBUG_KMS("Failed to query state of TMDS output buffers\n"); ++ return ret; ++ } ++ ++ *enabled = !(tmds_oen & DP_DUAL_MODE_TMDS_DISABLE); ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_get_tmds_output); ++ ++/** ++ * drm_dp_dual_mode_set_tmds_output - Enable/disable TMDS output buffers in the DP dual mode adaptor ++ * @type: DP dual mode adaptor type ++ * @adapter: I2C adapter for the DDC bus ++ * @enable: enable (as opposed to disable) the TMDS output buffers ++ * ++ * Set the state of the TMDS output buffers in the adaptor. For ++ * type2 this is set via the DP_DUAL_MODE_TMDS_OEN register. As ++ * some type 1 adaptors have problems with registers (see comments ++ * in drm_dp_dual_mode_detect()) we avoid touching the register, ++ * making this function a no-op on type 1 adaptors. ++ * ++ * Returns: ++ * 0 on success, negative error code on failure ++ */ ++int drm_dp_dual_mode_set_tmds_output(enum drm_dp_dual_mode_type type, ++ struct i2c_adapter *adapter, bool enable) ++{ ++ uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE; ++ ssize_t ret; ++ ++ if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) ++ return 0; ++ ++ ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_TMDS_OEN, ++ &tmds_oen, sizeof(tmds_oen)); ++ if (ret) { ++ DRM_DEBUG_KMS("Failed to %s TMDS output buffers\n", ++ enable ? "enable" : "disable"); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output); ++ ++/** ++ * drm_dp_get_dual_mode_type_name - Get the name of the DP dual mode adaptor type as a string ++ * @type: DP dual mode adaptor type ++ * ++ * Returns: ++ * String representation of the DP dual mode adaptor type ++ */ ++const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type) ++{ ++ switch (type) { ++ case DRM_DP_DUAL_MODE_NONE: ++ return "none"; ++ case DRM_DP_DUAL_MODE_TYPE1_DVI: ++ return "type 1 DVI"; ++ case DRM_DP_DUAL_MODE_TYPE1_HDMI: ++ return "type 1 HDMI"; ++ case DRM_DP_DUAL_MODE_TYPE2_DVI: ++ return "type 2 DVI"; ++ case DRM_DP_DUAL_MODE_TYPE2_HDMI: ++ return "type 2 HDMI"; ++ default: ++ WARN_ON(type != DRM_DP_DUAL_MODE_UNKNOWN); ++ return "unknown"; ++ } ++} ++EXPORT_SYMBOL(drm_dp_get_dual_mode_type_name); +diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c +index 855108e6e1bd..fe4df976f0b8 100644 +--- a/drivers/gpu/drm/drm_fb_helper.c ++++ b/drivers/gpu/drm/drm_fb_helper.c +@@ -1895,7 +1895,6 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, + int n, int width, int height) + { + int c, o; +- struct drm_device *dev = fb_helper->dev; + struct drm_connector *connector; + const struct drm_connector_helper_funcs *connector_funcs; + struct drm_encoder *encoder; +@@ -1914,7 +1913,7 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, + if (modes[n] == NULL) + return best_score; + +- crtcs = kzalloc(dev->mode_config.num_connector * ++ crtcs = kzalloc(fb_helper->connector_count * + sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL); + if (!crtcs) + return best_score; +@@ -1960,7 +1959,7 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper, + if (score > best_score) { + best_score = score; + memcpy(best_crtcs, crtcs, +- dev->mode_config.num_connector * ++ fb_helper->connector_count * + sizeof(struct drm_fb_helper_crtc *)); + } + } +diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c +index 6b43ae3ffd73..1616af209bfc 100644 +--- a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c ++++ b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c +@@ -72,7 +72,7 @@ static const char *const dsi_errors[] = { + "RX Prot Violation", + "HS Generic Write FIFO Full", + "LP Generic Write FIFO Full", +- "Generic Read Data Avail" ++ "Generic Read Data Avail", + "Special Packet Sent", + "Tearing Effect", + }; +diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c +index 8e579a8505ac..e7c1686e479c 100644 +--- a/drivers/gpu/drm/i915/intel_atomic.c ++++ b/drivers/gpu/drm/i915/intel_atomic.c +@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) + crtc_state->update_pipe = false; + crtc_state->disable_lp_wm = false; + crtc_state->disable_cxsr = false; +- crtc_state->wm_changed = false; ++ crtc_state->update_wm_pre = false; ++ crtc_state->update_wm_post = false; + crtc_state->fb_changed = false; + + return &crtc_state->base; +diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c +index e0b851a0004a..7de7721f65bc 100644 +--- a/drivers/gpu/drm/i915/intel_atomic_plane.c ++++ b/drivers/gpu/drm/i915/intel_atomic_plane.c +@@ -195,12 +195,10 @@ static void intel_plane_atomic_update(struct drm_plane *plane, + struct intel_plane_state *intel_state = + to_intel_plane_state(plane->state); + struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc; +- struct drm_crtc_state *crtc_state = +- drm_atomic_get_existing_crtc_state(old_state->state, crtc); + + if (intel_state->visible) + intel_plane->update_plane(plane, +- to_intel_crtc_state(crtc_state), ++ to_intel_crtc_state(crtc->state), + intel_state); + else + intel_plane->disable_plane(plane, crtc); +diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c +index 96ffcc541e17..50f5b0c975e3 100644 +--- a/drivers/gpu/drm/i915/intel_ddi.c ++++ b/drivers/gpu/drm/i915/intel_ddi.c +@@ -2309,6 +2309,12 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) + enum port port = intel_ddi_get_encoder_port(intel_encoder); + int type = intel_encoder->type; + ++ if (type == INTEL_OUTPUT_HDMI) { ++ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); ++ ++ intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); ++ } ++ + intel_prepare_ddi_buffer(intel_encoder); + + if (type == INTEL_OUTPUT_EDP) { +@@ -2375,6 +2381,12 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) + DPLL_CTRL2_DDI_CLK_OFF(port))); + else if (INTEL_INFO(dev)->gen < 9) + I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); ++ ++ if (type == INTEL_OUTPUT_HDMI) { ++ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); ++ ++ intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); ++ } + } + + static void intel_enable_ddi(struct intel_encoder *intel_encoder) +diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c +index 0104a06d01fd..7741efbd5e57 100644 +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -4796,7 +4796,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc) + + crtc->wm.cxsr_allowed = true; + +- if (pipe_config->wm_changed && pipe_config->base.active) ++ if (pipe_config->update_wm_post && pipe_config->base.active) + intel_update_watermarks(&crtc->base); + + if (atomic->update_fbc) +@@ -4843,7 +4843,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) + intel_set_memory_cxsr(dev_priv, false); + } + +- if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) ++ if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre) + intel_update_watermarks(&crtc->base); + } + +@@ -6210,6 +6210,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) + + intel_crtc_load_lut(crtc); + ++ intel_update_watermarks(crtc); + intel_enable_pipe(intel_crtc); + + assert_vblank_disabled(crtc); +@@ -11833,14 +11834,22 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, + plane->base.id, was_visible, visible, + turn_off, turn_on, mode_changed); + +- if (turn_on || turn_off) { +- pipe_config->wm_changed = true; ++ if (turn_on) { ++ pipe_config->update_wm_pre = true; ++ ++ /* must disable cxsr around plane enable/disable */ ++ if (plane->type != DRM_PLANE_TYPE_CURSOR) ++ pipe_config->disable_cxsr = true; ++ } else if (turn_off) { ++ pipe_config->update_wm_post = true; + + /* must disable cxsr around plane enable/disable */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) + pipe_config->disable_cxsr = true; + } else if (intel_wm_need_update(plane, plane_state)) { +- pipe_config->wm_changed = true; ++ /* FIXME bollocks */ ++ pipe_config->update_wm_pre = true; ++ pipe_config->update_wm_post = true; + } + + if (visible || was_visible) +@@ -11940,7 +11949,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, + } + + if (mode_changed && !crtc_state->active) +- pipe_config->wm_changed = true; ++ pipe_config->update_wm_post = true; + + if (mode_changed && crtc_state->enable && + dev_priv->display.crtc_compute_clock && +@@ -13453,12 +13462,12 @@ static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) + return true; + + /* wm changes, need vblank before final wm's */ +- if (crtc_state->wm_changed) ++ if (crtc_state->update_wm_post) + return true; + + /* + * cxsr is re-enabled after vblank. +- * This is already handled by crtc_state->wm_changed, ++ * This is already handled by crtc_state->update_wm_post, + * but added for clarity. + */ + if (crtc_state->disable_cxsr) +@@ -15958,6 +15967,18 @@ void intel_display_resume(struct drm_device *dev) + retry: + ret = drm_modeset_lock_all_ctx(dev, &ctx); + ++ /* ++ * With MST, the number of connectors can change between suspend and ++ * resume, which means that the state we want to restore might now be ++ * impossible to use since it'll be pointing to non-existant ++ * connectors. ++ */ ++ if (ret == 0 && state && ++ state->num_connector != dev->mode_config.num_connector) { ++ drm_atomic_state_free(state); ++ state = NULL; ++ } ++ + if (ret == 0 && !setup) { + setup = true; + +diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h +index 9d0770c23fde..3a30b37d6885 100644 +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -378,7 +379,7 @@ struct intel_crtc_state { + + bool update_pipe; /* can a fast modeset be performed? */ + bool disable_cxsr; +- bool wm_changed; /* watermarks are updated */ ++ bool update_wm_pre, update_wm_post; /* watermarks are updated */ + bool fb_changed; /* fb on any of the planes is changed */ + + /* Pipe source size (ie. panel fitter input size) +@@ -703,6 +704,10 @@ struct cxsr_latency { + struct intel_hdmi { + i915_reg_t hdmi_reg; + int ddc_bus; ++ struct { ++ enum drm_dp_dual_mode_type type; ++ int max_tmds_clock; ++ } dp_dual_mode; + bool limited_color_range; + bool color_range_auto; + bool has_hdmi_sink; +@@ -1351,6 +1356,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, + struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); + bool intel_hdmi_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config); ++void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); + + + /* intel_lvds.c */ +diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c +index 97a91e631915..c607217c13ea 100644 +--- a/drivers/gpu/drm/i915/intel_fbdev.c ++++ b/drivers/gpu/drm/i915/intel_fbdev.c +@@ -366,12 +366,12 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper, + uint64_t conn_configured = 0, mask; + int pass = 0; + +- save_enabled = kcalloc(dev->mode_config.num_connector, sizeof(bool), ++ save_enabled = kcalloc(fb_helper->connector_count, sizeof(bool), + GFP_KERNEL); + if (!save_enabled) + return false; + +- memcpy(save_enabled, enabled, dev->mode_config.num_connector); ++ memcpy(save_enabled, enabled, fb_helper->connector_count); + mask = (1 << fb_helper->connector_count) - 1; + retry: + for (i = 0; i < fb_helper->connector_count; i++) { +@@ -510,7 +510,7 @@ retry: + if (fallback) { + bail: + DRM_DEBUG_KMS("Not using firmware configuration\n"); +- memcpy(enabled, save_enabled, dev->mode_config.num_connector); ++ memcpy(enabled, save_enabled, fb_helper->connector_count); + kfree(save_enabled); + return false; + } +diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c +index 1ab6f687f640..3ddb4fac53fa 100644 +--- a/drivers/gpu/drm/i915/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/intel_hdmi.c +@@ -836,6 +836,22 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, + intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); + } + ++void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) ++{ ++ struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); ++ struct i2c_adapter *adapter = ++ intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); ++ ++ if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) ++ return; ++ ++ DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", ++ enable ? "Enabling" : "Disabling"); ++ ++ drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, ++ adapter, enable); ++} ++ + static void intel_hdmi_prepare(struct intel_encoder *encoder) + { + struct drm_device *dev = encoder->base.dev; +@@ -845,6 +861,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder) + const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; + u32 hdmi_val; + ++ intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); ++ + hdmi_val = SDVO_ENCODING_HDMI; + if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) + hdmi_val |= HDMI_COLOR_RANGE_16_235; +@@ -1143,6 +1161,8 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) + } + + intel_hdmi->set_infoframes(&encoder->base, false, NULL); ++ ++ intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); + } + + static void g4x_disable_hdmi(struct intel_encoder *encoder) +@@ -1168,27 +1188,42 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder) + intel_disable_hdmi(encoder); + } + +-static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) ++static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) + { +- struct drm_device *dev = intel_hdmi_to_dev(hdmi); +- +- if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) ++ if (IS_G4X(dev_priv)) + return 165000; +- else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) ++ else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) + return 300000; + else + return 225000; + } + ++static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, ++ bool respect_downstream_limits) ++{ ++ struct drm_device *dev = intel_hdmi_to_dev(hdmi); ++ int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); ++ ++ if (respect_downstream_limits) { ++ if (hdmi->dp_dual_mode.max_tmds_clock) ++ max_tmds_clock = min(max_tmds_clock, ++ hdmi->dp_dual_mode.max_tmds_clock); ++ if (!hdmi->has_hdmi_sink) ++ max_tmds_clock = min(max_tmds_clock, 165000); ++ } ++ ++ return max_tmds_clock; ++} ++ + static enum drm_mode_status + hdmi_port_clock_valid(struct intel_hdmi *hdmi, +- int clock, bool respect_dvi_limit) ++ int clock, bool respect_downstream_limits) + { + struct drm_device *dev = intel_hdmi_to_dev(hdmi); + + if (clock < 25000) + return MODE_CLOCK_LOW; +- if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) ++ if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) + return MODE_CLOCK_HIGH; + + /* BXT DPLL can't generate 223-240 MHz */ +@@ -1312,7 +1347,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, + * within limits. + */ + if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && +- hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && ++ hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && + hdmi_12bpc_possible(pipe_config)) { + DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); + desired_bpp = 12*3; +@@ -1352,10 +1387,35 @@ intel_hdmi_unset_edid(struct drm_connector *connector) + intel_hdmi->has_audio = false; + intel_hdmi->rgb_quant_range_selectable = false; + ++ intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; ++ intel_hdmi->dp_dual_mode.max_tmds_clock = 0; ++ + kfree(to_intel_connector(connector)->detect_edid); + to_intel_connector(connector)->detect_edid = NULL; + } + ++static void ++intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) ++{ ++ struct drm_i915_private *dev_priv = to_i915(connector->dev); ++ struct intel_hdmi *hdmi = intel_attached_hdmi(connector); ++ struct i2c_adapter *adapter = ++ intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); ++ enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); ++ ++ if (type == DRM_DP_DUAL_MODE_NONE || ++ type == DRM_DP_DUAL_MODE_UNKNOWN) ++ return; ++ ++ hdmi->dp_dual_mode.type = type; ++ hdmi->dp_dual_mode.max_tmds_clock = ++ drm_dp_dual_mode_max_tmds_clock(type, adapter); ++ ++ DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", ++ drm_dp_get_dual_mode_type_name(type), ++ hdmi->dp_dual_mode.max_tmds_clock); ++} ++ + static bool + intel_hdmi_set_edid(struct drm_connector *connector, bool force) + { +@@ -1371,6 +1431,8 @@ intel_hdmi_set_edid(struct drm_connector *connector, bool force) + intel_gmbus_get_adapter(dev_priv, + intel_hdmi->ddc_bus)); + ++ intel_hdmi_dp_dual_mode_detect(connector); ++ + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); + } + +diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c +index 3425d8e737b3..54ab023427c7 100644 +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -3845,6 +3845,8 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); + ++ memset(active, 0, sizeof(*active)); ++ + active->pipe_enabled = intel_crtc->active; + + if (active->pipe_enabled) { +diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c +index 0b42ada338c8..bd322d8fba40 100644 +--- a/drivers/gpu/drm/i915/intel_psr.c ++++ b/drivers/gpu/drm/i915/intel_psr.c +@@ -280,7 +280,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) + * with the 5 or 6 idle patterns. + */ + uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); +- uint32_t val = 0x0; ++ uint32_t val = EDP_PSR_ENABLE; ++ ++ val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; ++ val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; + + if (IS_HASWELL(dev)) + val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; +@@ -288,14 +291,50 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) + if (dev_priv->psr.link_standby) + val |= EDP_PSR_LINK_STANDBY; + +- I915_WRITE(EDP_PSR_CTL, val | +- max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | +- idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | +- EDP_PSR_ENABLE); ++ if (dev_priv->vbt.psr.tp1_wakeup_time > 5) ++ val |= EDP_PSR_TP1_TIME_2500us; ++ else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) ++ val |= EDP_PSR_TP1_TIME_500us; ++ else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) ++ val |= EDP_PSR_TP1_TIME_100us; ++ else ++ val |= EDP_PSR_TP1_TIME_0us; ++ ++ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) ++ val |= EDP_PSR_TP2_TP3_TIME_2500us; ++ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) ++ val |= EDP_PSR_TP2_TP3_TIME_500us; ++ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) ++ val |= EDP_PSR_TP2_TP3_TIME_100us; ++ else ++ val |= EDP_PSR_TP2_TP3_TIME_0us; ++ ++ if (intel_dp_source_supports_hbr2(intel_dp) && ++ drm_dp_tps3_supported(intel_dp->dpcd)) ++ val |= EDP_PSR_TP1_TP3_SEL; ++ else ++ val |= EDP_PSR_TP1_TP2_SEL; ++ ++ I915_WRITE(EDP_PSR_CTL, val); ++ ++ if (!dev_priv->psr.psr2_support) ++ return; ++ ++ /* FIXME: selective update is probably totally broken because it doesn't ++ * mesh at all with our frontbuffer tracking. And the hw alone isn't ++ * good enough. */ ++ val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; ++ ++ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) ++ val |= EDP_PSR2_TP2_TIME_2500; ++ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) ++ val |= EDP_PSR2_TP2_TIME_500; ++ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) ++ val |= EDP_PSR2_TP2_TIME_100; ++ else ++ val |= EDP_PSR2_TP2_TIME_50; + +- if (dev_priv->psr.psr2_support) +- I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE | +- EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100); ++ I915_WRITE(EDP_PSR2_CTL, val); + } + + static bool intel_psr_match_conditions(struct intel_dp *intel_dp) +diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c +index e26dcdec2aba..05229b960e0c 100644 +--- a/drivers/gpu/drm/imx/imx-drm-core.c ++++ b/drivers/gpu/drm/imx/imx-drm-core.c +@@ -25,6 +25,7 @@ + #include + #include + #include ++#include