[gentoo-commits] proj/qemu-kvm:qemu-kvm-1.1.2-gentoo commit in: target-mips/

[gentoo-commits] proj/qemu-kvm:qemu-kvm-1.1.2-gentoo commit in: target-mips/

[Doug Goldstein]

commit:     a9ff62518fd8c969636d20cd12f84a44f00a08df
Author:     Nathan Froyd <froydnj <AT> codesourcery <DOT> com>
AuthorDate: Thu Jun  7 15:04:14 2012 +0000
Commit:     Doug Goldstein <cardoe <AT> gentoo <DOT> org>
CommitDate: Wed Nov 21 21:25:09 2012 +0000
URL:        http://git.overlays.gentoo.org/gitweb/?p=proj/qemu-kvm.git;a=commit;h=a9ff6251

MIPS: Correct FCR0 initialization

 This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:

	madd.d	$f2,$f4,$f2,$f6

 Here's Nathan's original analysis of the problem:

"QEMU essentially does:

  d = find_cpu (cpu_string)	// get CPU definition
  fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."

 I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.

Signed-off-by: Maciej W. Rozycki <macro <AT> codesourcery.com>
Reviewed-by: Richard Henderson <rth <AT> twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel <AT> gmail.com>
(cherry picked from commit f1cb0951c5298753652a73cfd8efc0b1a82f37de)

---
 target-mips/translate.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 5ed58f6..8ff1fab 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12783,6 +12783,7 @@ void cpu_state_reset(CPUMIPSState *env)
     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
+    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
     env->insn_flags = env->cpu_model->insn_flags;
 
 #if defined(CONFIG_USER_ONLY)

[gentoo-commits] proj/qemu-kvm:qemu-kvm-1.1.2-gentoo commit in: target-mips/

[Doug Goldstein]

commit:     91ef50cf03763fbc9ce0a4412b99b72d2a141220
Author:     陳韋任 (Wei-Ren Chen) <chenwj <AT> iis <DOT> sinica <DOT> edu <DOT> tw>
AuthorDate: Wed Nov 14 02:49:55 2012 +0000
Commit:     Doug Goldstein <cardoe <AT> gentoo <DOT> org>
CommitDate: Wed Nov 21 21:31:00 2012 +0000
URL:        http://git.overlays.gentoo.org/gitweb/?p=proj/qemu-kvm.git;a=commit;h=91ef50cf

target-mips: fix wrong microMIPS opcode encoding

While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <chenwj <AT> iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien <AT> aurel32.net>
(cherry picked from commit 6801038bc52d61f81ac8a25fbe392f1bad982887)

---
 target-mips/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8ff1fab..6932c28 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9463,7 +9463,7 @@ enum {
 
     /* bits 13..12 for 0x32 */
     MULT_ACC = 0x0,
-    MULTU_ACC = 0x0,
+    MULTU_ACC = 0x1,
 
     /* bits 15..12 for 0x2c */
     SEB = 0x2,