From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lists.gentoo.org ([140.105.134.102] helo=robin.gentoo.org) by nuthatch.gentoo.org with esmtp (Exim 4.62) (envelope-from ) id 1Hk9a9-00086j-NN for garchives@archives.gentoo.org; Sat, 05 May 2007 02:01:10 +0000 Received: from robin.gentoo.org (localhost [127.0.0.1]) by robin.gentoo.org (8.14.0/8.14.0) with SMTP id l451wiJI016298; Sat, 5 May 2007 01:58:44 GMT Received: from ciao.gmane.org (main.gmane.org [80.91.229.2]) by robin.gentoo.org (8.14.0/8.14.0) with ESMTP id l451wifZ016284 for ; Sat, 5 May 2007 01:58:44 GMT Received: from list by ciao.gmane.org with local (Exim 4.43) id 1Hk9Xh-0000lj-3v for gentoo-amd64@lists.gentoo.org; Sat, 05 May 2007 03:58:37 +0200 Received: from ip68-230-67-248.ph.ph.cox.net ([68.230.67.248]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sat, 05 May 2007 03:58:37 +0200 Received: from 1i5t5.duncan by ip68-230-67-248.ph.ph.cox.net with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sat, 05 May 2007 03:58:37 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: gentoo-amd64@lists.gentoo.org From: Duncan <1i5t5.duncan@cox.net> Subject: [gentoo-amd64] Re: [OT] AGPART Date: Sat, 5 May 2007 01:58:29 +0000 (UTC) Message-ID: References: <20070504170035.8E51699466@mail.ilievnet.com> <463B6F3A.9050000@gentoo.org> Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-Id: Gentoo Linux mail X-BeenThere: gentoo-amd64@gentoo.org Reply-to: gentoo-amd64@lists.gentoo.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Complaints-To: usenet@sea.gmane.org X-Gmane-NNTP-Posting-Host: ip68-230-67-248.ph.ph.cox.net User-Agent: Pan/0.128 (SR/CL: Leitmotiv: Toynbee Idea) Sender: news X-Archives-Salt: f96b0a9e-fe34-41bc-a101-9a0a0d0534ef X-Archives-Hash: f6aa20e500e87ca81a79fc5ab1f8f504 Jeffrey Gardner posted 463B6F3A.9050000@gentoo.org, excerpted below, on Fri, 04 May 2007 12:36:58 -0500: > Processor type and features > [ ] IOMMU support Note that for AMD64, if you have >3.5 gig memory, you'll WANT IOMMU support, which uses the APGART hardware on AMD. On Intel, they don't have a hardware IOMMU but the kernel emulates it, using the same basic options, so I believe you'll want it there as well. Only four gig of memory is addressable from legacy 32-bit PCI devices, and there's a memory hole at the top of 4-gig memory (so beyond 3.5 gig) in ordered to allow device i/o memory access. With the correct BIOS settings, the machine will remap the unavailable memory behind that memory hole above 4 gig, but it and any memory you had beyond 4 gig already will not be directly accessible to DMA and the like from those legacy 32-bit PCI devices. IOMMU = input/output memory management unit. The hardware device maps high memory onto accessible addresses in the memory hole for the devices that need it, and of course the software emulation necessary for Intel machines does the same thing. Without that IOMMU, access to that > 4 gig area (because of the memory hole, to memory above ~3.5 gig) will be limited, and much slower for some devices if they work at all. Here, I simply cannot boot without IOMMU support (unless I disable part of my memory), as the kernel panics when it tries to read my hard drives. Apparently, either the SATA chipset they use or the kernel drivers supporting them are legacy 32-bit, and without the IOMMU, they simply cannot see the memory they are supposed to be DMAing stuff into. Of course, if you are still on legacy 32-bit x86 or have < 3.5 gig of memory (or are on a different arch entirely), the rules are somewhat different. I'm not sure how the IOMMU may be used there, or how much attempting to do without it might slow things down. -- Duncan - List replies preferred. No HTML msgs. "Every nonfree program has a lord, a master -- and if you use the program, he is your master." Richard Stallman -- gentoo-amd64@gentoo.org mailing list